Numerical Study on Shape Transformation of Silicon Trenches by High-Temperature Hydrogen Annealing

Sudoh, Koichi; Iwasaki, Hiroshi; Kuribayashi, Hitoshi; Hiruta, Reiko; Shimizu, Ryosuke

doi:10.1143/jjap.43.5937

Cited by 46 publications

(43 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Inset in the Fig.4 shows the result of such fitting which gives the value of characteristic wavelength 2.9 μm and corresponds to the value of D s = 9 10 -7 cm 2 /s. This surface diffusivity value is in a very good agreement with the value of 10 -6 cm 2 /s obtained from measurements of the evolution of the shape of Si trenches annealed in H 2 at 10 torr (11). It should be noted that characteristic cutoff frequency for thermal smoothing depends weakly on annealing time and surface diffusivity.…”

Section: High Temperature Annealing In the Smart Cut Technologysupporting

confidence: 88%

(Invited) Recent Advances in the Smart Cut Technology for CMOS Applications

et al. 2010

View full text Add to dashboard Cite

New challenges for SOI wafer technology arise due to introduction of fully depleted CMOS architecture. Top Si layer thickness uniformity and reduced BOX thickness are the most demanding parameters. Replacement of CMP process in the Smart Cut SOI technology by high temperature annealing in inert atmosphere allows to meet wafer requirements for 22 nm technology. New SOI Requirements for Emerging CMOS ArchitecturesCMOS device roadmap predicts transition from current partially depleted device architecture to fully depleted devices at 22 nm technology node. Fully depleted (FD) SOI IC architecture is one of the most promising technology platforms which addresses simultaneously the needs of consumer mobile applications by offering very low stand-by power consumption while enabling a high device performance at lower Vdd than the bulk CMOS technologies. (FD)MOSFETs demonstrate an improvement of many device characteristics, especially for low power applications (1), enhance the SRAM cell stability due to decreasing random doping fluctuations. FD MOSFET is also a key basic element of floating body cell memory, which is a promising alternative to high density SRAM for memory intensive microcomputing applications (2).Advanced FD devices, such as double gate planar MOSFET, built on SOI wafers require wafers with extremely thin Si top layer (UTSOI) as well as ultra thin BOX layer, called UTBOX SOI. To sustain good electrostatic control of the channel and to keep back-gate voltages reasonably low, top Si layer thickness has to be in the 5-10 nm range (3). BOX thickness needs to be less than 25 nm approaching sub 10 nm layers for further technology nodes. Threshold voltage of FD MOSFET directly depends on Si thickness. This imposes extremely tight requirements on layer thickness uniformity and defectivity. Computer simulations of 22 nm devices show that for double gate MOSFETs with BOX thickness of 10 nm and ground plane, standard deviation of top Si layer thickness should be below 2 Å (3). Recent advances in the Unibond™ process, such as optimization of implantation conditions and replacement of CMP finishing by thermal smoothing technology, demonstrate capability of production of SOI wafers with top Si thickness uniformity +/-1.5 nm (4). Figure 1 shows typical SOI thickness uniformity data evidencing tight wafer to wafer and within wafer thickness uniformity. High temperature annealing in non-oxidized atmosphere leads to reduction of top Si surface roughness while maintaining excellent thickness uniformity. In the paper, we will discuss the mechanism of roughness improvement during high temperature annealing as well as the limits of stability of SOI system during such anneals.Standard Unibond process is based on hydrophilic bonding of two Si wafer surfaces covered by silicon dioxide. Water molecules absorbed on the surface of SiO 2 increase bonding energy at room temperature and assure low bonding defect density.

show abstract

Section: High Temperature Annealing In the Smart Cut Technologysupporting

confidence: 88%

(Invited) Recent Advances in the Smart Cut Technology for CMOS Applications

et al. 2010

View full text Add to dashboard Cite

show abstract

“…This theory has provided fundamental interpretations on corner rounding of Si microstructures during hydrogen annealing. [17][18][19] However, the theory for isotropic surfaces cannot be used to explain the evolution of the faceted voids observed in this investigation. Here, we invoke a modeling for the shape evolution of a faceted void introduced by Kitayama et al 20 For completely faceted polyhedral structures, we can consider the mean chemical potential of each facet, which depends on the local facet configuration instead of the Gibbs-Thomson chemical potential.…”

Section: Discussionmentioning

confidence: 99%

Void shape evolution and formation of silicon-on-nothing structures during hydrogen annealing of hole arrays on Si(001)

Sudoh

Iwasaki

Hiruta

et al. 2009

Journal of Applied Physics

View full text Add to dashboard Cite

We have studied the structural evolution of voids in the Si substrate and the formation of silicon-on-nothing ͑SON͒ structures upon spontaneous reshaping of square arrays of cylindrical holes on Si͑001͒ substrates by hydrogen annealing. Vertically elongated voids covered with ͕111͖, ͕100͖, ͕110͖, and ͕113͖ facets are initially formed by the closure of the hole inlets. This step is followed by volume preserving shape changes of the faceted voids in the bulk Si. In situations where the hole-hole separation is sufficiently small, void coalescence occurs due to the shape changes of individual voids, leading to the formation of a SON structure. Until void coalescence, the shapes of individual voids change without being affected by the adjacent voids. Numerical simulations of the shape change of a completely faceted void via solely surface diffusion have been performed and have reproduced the observed shape change.

show abstract

“…For isotropic materials, surface diffusion and evaporation-condensation contribute to the fundamental surface mass transport mechanisms [25]. However, for annealing temperatures less than 1100 C, surface diffusion is dominant in profile transformation [26]. In our applications, the temperature is around 1050 C, which is compatible with typical microfabrication, and only the surface diffusion mechanism is considered.…”

Section: Process Characteristicsmentioning

confidence: 99%