NVM Way Allocation Scheme to Reduce NVM Writes for Hybrid Cache Architecture in Chip-Multiprocessors

Choi, Ju Hee; Park, Gi-Ho

doi:10.1109/tpds.2017.2689010

Cited by 26 publications

(9 citation statements)

References 31 publications

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“…The effects of PVs is not included in the above formulations. To calculate the cache reliability in terms of retention, read disturbance, and write failure considering PVs, we simply use PV affected probability given in ( 18), (21), and ( 24), instead of probabilities in ( 9), (12), and (15), respectively, for calculating the total cache failure probability.…”

Section: B Total Cache Failure Probabilitymentioning

confidence: 99%

“…𝑅𝑒𝑡𝑒𝑛𝑡𝑖𝑜𝑛 𝑓 𝑎𝑖𝑙𝑢𝑟𝑒 (i.e., the content of a cell flips during its idle time) [6], [11], [13], 𝑟𝑒𝑎𝑑 𝑑𝑖𝑠𝑡𝑢𝑟𝑏𝑎𝑛𝑐𝑒 (i.e., unintentional flip of a cell due to applying read current during a read access) [? ], [17]- [19], and 𝑤𝑟𝑖𝑡𝑒 𝑓 𝑎𝑖𝑙𝑢𝑟𝑒 (i.e., unsuccessful write operation due to inability of a cell to switch) [3], [20], [21] are the main sources of errors in STT-MRAM LLCs. Stochastic switching behavior of magnetic field direction in STT-MRAM cells is the source of the mentioned error types [3], [22], [23].…”

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confidence: 99%

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A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches

2020

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𝑆 𝑝𝑖𝑛-𝑇𝑟𝑎𝑛𝑠 𝑓 𝑒𝑟 𝑇 𝑜𝑟𝑞𝑢𝑒 𝑀𝑎𝑔𝑛𝑒𝑡𝑖𝑐 𝑅 𝐴𝑀 (STT-MRAM) is known as the most promising replacement for SRAM technology in large 𝐿𝑎𝑠𝑡-𝐿𝑒𝑣𝑒𝑙 𝐶𝑎𝑐ℎ𝑒 memories (LLCs). Despite its high-density, non-volatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAMbased cache memory suffers from high error rates mainly due to 𝑟𝑒𝑡𝑒𝑛𝑡𝑖𝑜𝑛 𝑓 𝑎𝑖𝑙𝑢𝑟𝑒, 𝑟𝑒𝑎𝑑 𝑑𝑖𝑠𝑡𝑢𝑟𝑏𝑎𝑛𝑐𝑒, and 𝑤𝑟𝑖𝑡𝑒 𝑓 𝑎𝑖𝑙𝑢𝑟𝑒. Existing studies are limited to estimate the rate of 𝑜𝑛𝑙 𝑦 one or two of these error types for STT-MRAM cache. However, the overall vulnerability of STT-MRAM caches, which its estimation is a must to design cost-efficient reliable caches, has not been offered in none of previous studies.In this paper, we propose a system-level framework for reliability exploration and characterization of errors behavior in STT-MRAM caches. To this end, we formulate the cache vulnerability considering the inter-correlation of the error types including retention failure, read disturbance, and write failure as well as the dependency of error rates to workloads behavior and 𝑃𝑟𝑜𝑐𝑒𝑠𝑠 𝑉 𝑎𝑟𝑖𝑎𝑡𝑖𝑜𝑛𝑠 (PVs). Our analysis reveals that STT-MRAM cache vulnerability is highly workload-dependent and varies by orders of magnitude in different cache access patterns. Our analytical study also shows that this vulnerability divergence significantly increases by process variations in STT-MRAM cells. To take the effects of system workloads and PVs into account, we implement the error types in gem5 full-system simulator. The experimental results using a comprehensive set of multi-programmed workloads from SPEC CPU2006 benchmark suite on a quad-core processor show that the total error rate in a shared STT-MRAM LLC varies by 32.0x for different workloads. A further 6.5x vulnerability variation is observed when considering PVs in the STT-MRAM cells. In addition, the contribution of each error type in total LLC vulnerability highly varies in different cache access patterns and moreover, error rates are differently affected by PVs. The proposed analytical and empirical studies can significantly help system architects for efficient utilization of error mitigation techniques and designing highly reliable and low-cost STT-MRAM LLCs.

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Section: B Total Cache Failure Probabilitymentioning

confidence: 99%

mentioning

confidence: 99%

A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches

2020

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“…Therefore, for mobile devices that run on batteries, efficient power optimization techniques are highly in demand as the sizes of transistors progressively decreases. The introduction of MCA trades-off performance for power expanding the fraction of chip area and on-chip power that caches account for [41,70,78]. Consequently, this increase in chip area and power can lead to thermal and reliability issues and therefore, reducing cache power consumption can avoid this and increase the power budget available for actual computation.…”

Section: Reducing Power Consumption In the Cache Architecturementioning

confidence: 99%

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Ofori-Attah¹,

Wang²,

Agyeman³

2018

EAI Endorsed Transactions on Industrial Networks and Intelligen

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Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, with manycore integration set to be heading towards its thousands, power consumption and temperature increases per time, meaning the number of active nodes must be reduced drastically. Therefore, optimized techniques are demanded for continuous advancement in technology. Existing efforts try to overcome this challenge by activating nodes from different parts of the chip at the expense of communication latency. Other efforts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-off performance for power. We found out that, for a significant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components. Especially, the memory hierarchy and the interconnect. Power consumption can be minimized by, reducing the size of high leakage power dissipating elements, turning-off idle resources and integrating power saving materials.

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“…Choi et al [39] proposed a cache way allocation scheme which effectively allocates SRAM and NVM ways by considering the impact of NVM writes by the landfill operation. Unlike other schemes which allocates write-intensive blocks to the SRAM ways, this scheme reduces the NVM write counts through a two-step approach.…”

Section: Resizing Cache Sizementioning

confidence: 99%

A Survey of Low Power Design Techniques for Last Level Caches

Ofori-Attah

Wang

Agyeman

2018

Applied Reconfigurable Computing. Architectures, Tools, and Applications

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The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming element. Consequently, there have been several efforts towards reducing power consumption in LLCs. This paper presents a survey of recent contribution towards reducing power consumption in the LLC.

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NVM Way Allocation Scheme to Reduce NVM Writes for Hybrid Cache Architecture in Chip-Multiprocessors

Cited by 26 publications

References 31 publications

A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches

A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

A Survey of Low Power Design Techniques for Last Level Caches

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