nZDC

Didehban, Moslem; Shrivastava, Aviral

doi:10.1145/2897937.2898054

Cited by 64 publications

(6 citation statements)

References 17 publications

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“…In [5], each element is subject to small 300-long fault campaign for each of the ten applications collected from both MiBench and SPEC-Int 2006 benchmark suites. A similar gem5-based fault injection framework is described in [4].…”

Section: Related Work In Fault Injection Frameworkmentioning

confidence: 99%

“…Further, such approaches typically report low simulation performances of up to 3 MIPS [7], which restricts the number and the complexity of fault injection campaigns. While some works consider a single ISA [7], others use only in-house applications [10] or bare-metal implementations [5,3,4]. Different from the above works, SOFIA offers four novel non-intrusive fault injection techniques that provide engineers with flexibility and full control over the fault injection process, allowing to disentangle the cause and effect relationship between an injected fault and the occurrence of possible soft errors, targeting a specific critical application, operating system or API structure/function.…”

Section: Related Work In Fault Injection Frameworkmentioning

confidence: 99%

“…In this regard, the high cost and time inherent to hardware-based fault injection methods make more efficient simulation-based fault injection frameworks key to test reliability. Most fault injection simulators available in the literature offer a restricted number of fault injection exploration capabilities such as injection of bit-flips in memory [3], general-purpose registers and some other CPU components (e.g., load/store queue) [4,5]. However, with the growing complexity of both processor and software architectures, more appropriate fault injection techniques and tools are required.…”

Section: Introductionmentioning

confidence: 99%

“…SOFIA integrates the proposed fault injection techniques along with several facilities (e.g., error tracer module), which enable to identify and classify the effects of soft errors on the system behavior, considering both hardware and software architectures. SOFIA is based on the Multicore Developer (M*DEV) virtual platform 4 , and its implementation is highly autonomous and requires little human interaction, after its configuration. This work is organized as follows, in Section 2 we review relevant works regarding simulation frameworks and soft error analysis.…”

Section: Introductionmentioning

confidence: 99%

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Efficient Soft Error Vulnerability Analysis Using Non-intrusive Fault Injection Techniques

Bandeira¹,

Rosa²,

Reis³

et al. 2020

IFIP Advances in Information and Communication Technology

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Electronic computing systems are integrating modern multicore processors and GPUs aiming to perform complex software stacks in different life-critical systems, including health devices and emerging self-driving cars. Such systems are expected to experience at least one soft error per day in the near future, which may lead to life-threatening failures. To prevent these failures, critical system must be tested and verified while under realistic workloads. This paper presents four novel non-intrusive fault injection techniques that enable full fault injection control and inspection of multicore systems behavior in the presence of faults. Proposed techniques were integrated into a fault injection framework and verified through a real automotive case study with up to 43 billions instructions. Results show that compared to traditional methods, the new techniques can increase the efficiency of fault injection campaigns during early development phase by 32.28%.

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Section: Related Work In Fault Injection Frameworkmentioning

confidence: 99%

Section: Related Work In Fault Injection Frameworkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Efficient Soft Error Vulnerability Analysis Using Non-intrusive Fault Injection Techniques

Bandeira¹,

Rosa²,

Reis³

et al. 2020

IFIP Advances in Information and Communication Technology

View full text Add to dashboard Cite

show abstract

“…A common approach to achieve instruction-level redundancy is to duplicate the existing instructions of the program and execute them on separate shadow CPU registers [15]- [17]. This means that half of the CPU registers are used for calculations in the program, while the other half are shadow registers.…”

Section: Introductionmentioning

confidence: 99%

Utilizing Parity Checking to Optimize Soft Error Detection Through Low-Level Reexecution

De Blaere,

Vankeirsbilck,

Boydens

2023

IEEE Trans. Rel.

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Higher component density, lower voltage levels and higher transistor counts increase programmable systems' susceptibility to transient faults. At the same time, the adoption of embedded systems in many safety-critical and mission-critical systems makes their reliability of utmost importance. Softwareimplemented error detection techniques can be utilized to protect these systems as an alternative to less flexible and costlier hardware solutions like redundant hardware or fully duplicated systems. One of these techniques is the low-level re-executionbased technique called DETECTOR, which matches the error reduction capabilities of other state-of-the-art techniques while utilizing only three reserved CPU registers. This is in contrast to other techniques, which required a large number of CPU registers to be reserved, making them unusable for some programs. This paper provides an optimization of DETECTOR by combining parity checking with DETECTOR's re-execution mechanism. The technique, called P-DETECTOR, is validated extensively on multiple data processing and I/O-driven case studies and compared to the state-of-the-art. The results show that, compared to an unprotected system, the P-DETECTOR technique reduces the percentage of faults resulting in a corrupted output by 93.76% for control flow errors and by 87.89% for data flow errors, outperforming DETECTOR and matching other state-ofthe-art techniques like RACFED, SWIFT and FDSC.

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Using Hardware-In-Loop-Based Fault Injection to Determine the Effects of Control Flow Errors in Industrial Control Programs

Vankeirsbilck

Hallez

Boydens

2020

Lecture Notes in Computer Science

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Embedded systems, which are at the core of many small scale and large scale machines, are affected by external disturbances which can introduce control flow errors. These control flow errors can affect the control program executing on the embedded system, potentially causing sensor signals to be misinterpreted or actuators being miscontrolled. Software-implemented control flow error detection techniques have existed for many years, although there is little literature about these techniques being tested on input/output-driven programs. This paper presents a hardware-in-loop-based fault injection campaign performed on a typical industrial setting, i.e. a small scale factory. Thanks to hardware-in-loop simulation, we can perform the fault injection campaign without the risk of breaking a mechanical or an electrical part. For our fault injection campaign, we considered both the unprotected control program and the version protected with our RACFED error detection technique. The results show that up to 58 % of the injected control flow errors can affect the unprotected control program in a dangerous manner. Implementing RACFED clearly lowers this percentage to less than 4 %, showing this technique can be used in industrial settings.

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nZDC

Cited by 64 publications

References 17 publications

Efficient Soft Error Vulnerability Analysis Using Non-intrusive Fault Injection Techniques

Efficient Soft Error Vulnerability Analysis Using Non-intrusive Fault Injection Techniques

Utilizing Parity Checking to Optimize Soft Error Detection Through Low-Level Reexecution

Using Hardware-In-Loop-Based Fault Injection to Determine the Effects of Control Flow Errors in Industrial Control Programs

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