Observation of Mobility Enhancement in Strained Si and SiGe Tri-Gate MOSFETs with Multi-Nanowire Channels Trimmed by Hydrogen Thermal Etching

Tezuka, T.; Toyoda, Eiji; Nakaharai, Shu; Hirashita, N.; Sugiyama, N.; Taoka, Noriyuki; Yamashita, Yoshimi; Kiso, O.; Harada, M.; Yamamoto, Tetsuya; Takagi, Shinichi

doi:10.1109/iedm.2007.4419092

Cited by 32 publications

(25 citation statements)

References 5 publications

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“…Thus, strain engineering is used to enhance the performance of both n-channel MOS and p-channel MOS devices in modern CMOS nodes below 90 nm [14], [15]. For planar devices and SOI, there has been extensive research on the effects of strain as a performance booster [16]- [19], and recently, this interest has extended to silicon nanowires [12], [20]. Uniaxial compressive strain is found to enhance performance in silicon nanowire pMOSFETs in [21], whereas uniaxial tensile strain enhancement is used as a booster for tri-gate nMOSFETs [22].…”

Section: Strain As Booster Of Carrier Mobilitymentioning

confidence: 99%

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

Moselund

Najmzadeh

Dobrosz

et al. 2010

IEEE Trans. Electron Devices

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Abstract-This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measured during processing is discussed. The strain profile in silicon nanowires is evaluated by Raman spectroscopy both before device gate stack fabrication (tensile strains of up to 2.5% are measured) and by measurement through the polysilicon gate on completed electrically characterized devices. Drain current boosting in bended n-channels is investigated as a function of the transistor operation regime, and it is shown that the enhancement depends on the effective electrical field. The maximum observed electron mobility enhancement is on the order of 100% for a gate bias near the threshold voltage. Measurements of stress through the full gate stack and experimental device characteristics of the same transistor reveal a stress of 600 MPa and corresponding improvements of the normalized drain current, normalized transconductance, and low-field mobility by 34% (at maximum gate overdrive), 50% (at g max ), and 53%, respectively, compared with a reference nonstrained device at room temperature. Finally, it is found that, at low temperatures, the low-field mobility is much higher in bended devices, compared with nonbended devices.

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Section: Strain As Booster Of Carrier Mobilitymentioning

confidence: 99%

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

Moselund

Najmzadeh

Dobrosz

et al. 2010

IEEE Trans. Electron Devices

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“…However, experimental NWs are frequently doped and the mobility can strongly be reduced due to scattering on ionized impurities. The large experimental mobilities for 110 SiNWs with d NW >10 nm, on the other hand, can be explained by strain effects [32], [39], [45], [46], which have not been accounted for in our model. Nevertheless, the model in its present form can be used as a reference for benchmarking SiNW technologies.…”

Section: Low-field Mobility Modelmentioning

confidence: 85%

Empirical Model for the Effective Electron Mobility in Silicon Nanowires

Granzner

Polyakov

Schippel

et al. 2014

IEEE Trans. Electron Devices

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An empirical model for the effective electron mobility in silicon nanowires (SiNWs) is presented. The model is based on published mobility data from numerical simulations of electron transport in SiNWs with different cross sections. Both phonon scattering and surface roughness scattering as well as the impact of the effective vertical field are considered. A comparison with a variety of experimental mobility data from the literature shows that the model can be treated as a reference for benchmarking different NW technologies. The effective field dependence is modeled by a simple expression making our mobility model very efficient for the use in numerical device simulators or in analytical MOSFET models. Index Terms-Effective field, empirical model, mobility, MOSFET, phonon scattering, silicon nanowires (SiNWs), surface roughness (SR).

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“…In terms of sub-12 nm FETs, recent studies have ranged from carbon nanotube to graphene devices, 9 nanowire Si and SiGe FETs, 10 and Ge 11 and InGaAs FETs. 12 Si/SiGe double quantum dot structures, laterally coupled by use of Coulomb blockade barriers involving spin-based quantum computing, have also been reported.…”

Section: Scaling Of Sws-qdc-fets To 9 Nm and Integration With Cmos Bimentioning

confidence: 99%

“…This enables processing of two or more bits simultaneously. [1][2][3] In a two-quantum-well system, state (00) is represented by no electrons, or their wavefunctions, located in either well; state (01) is represented by electrons in well W2; state (11) is represented by electrons in both wells, W2 and W1; and state (10) is represented by electrons in well W1. The assignment of states can be changed, depending on the application.…”

Section: Introductionmentioning

confidence: 99%

Si and InGaAs Spatial Wavefunction-Switched (SWS) FETs with II–VI Gate Insulators: An Approach to the Design and Integration of Two-Bit SRAMs and Binary CMOS Logic

Jain

Chan

Lingalugari

et al. 2015

Journal of Elec Materi

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Electron wavefunctions are switched spatially from one quantum well to another by varying the gate voltage V g in spatial wavefunction-switched (SWS) field-effect transistors (FETs), which comprise two or more coupled quantum wells serving as the transport channel. This is shown for Si/SiGe and InGaAs/AlInAs quantum well systems. The presence of charge in a particular well or channel is used to encode four states 00, 01, 10, 11. This unique property is used for two-bit processing, resulting in compact two-bit static random-access memory devices. Experimental data including capacitance-voltage peaks in Si and InGaAs multiple quantum well SWSFETs has verified the SWS phenomenon. Replacing quantum wells by an array of cladded quantum dots, forming a quantum dot superlattice (QDSL) layer, enhances the contrast and noise margin in SWS-FETs. This paper reports I-V and C-V characteristics for a fabricated twin-drain SWS-quantum dot channel (QDC) FET comprising four layers of self-assembled SiO x -Si quantum dots. SWS-QDC-FETs are shown to be scalable to $9 nm, and comprise four layers of cladded quantum dots with an array of 3 9 3 forming the channel.

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Observation of Mobility Enhancement in Strained Si and SiGe Tri-Gate MOSFETs with Multi-Nanowire Channels Trimmed by Hydrogen Thermal Etching

Cited by 32 publications

References 5 publications

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

Empirical Model for the Effective Electron Mobility in Silicon Nanowires

Si and InGaAs Spatial Wavefunction-Switched (SWS) FETs with II–VI Gate Insulators: An Approach to the Design and Integration of Two-Bit SRAMs and Binary CMOS Logic

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