Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization

Abstract

Buffered clock tree synthesis (CTS) is increasingly critical as VLSI technology continually scales down. Many researches have been done on this topic due to its key role in CTS, but current approaches either lack the obstacle-avoiding functionality or lead to large clock latency and/or skew. This paper presents a new obstacle-avoiding CTS approach with separate clock tree construction and buffer insertion stages based on an integral view to explore the global optimization space. Aiming at skew optimization under constraints of slew and obstacles, our CTS approach features the clock tree construction stage with the obstacle-aware topology generation algorithm called OBB, balanced insertion of candidate buffer positions, and a fast heuristic buffer insertion algorithm. Experimental results show the effectiveness of our CTS approach with significantly improved skew and latency than [6] by 46% and 63% on average, and 15.3% reduction in skew than [5]. Our OBB heuristic obtains 36% improvement in skew than the classic balanced bipartition algorithm (BB) in [9].

Fast synthesis of low power clock trees based on register clustering

“…In this stage, the allocated LCBs become the registers of the top-level tree, and the capacitance of each register is equal to the input capacitance of the corresponding LCB. The CTS approach in [6] is adopted to utilize the toplevel clock tree. We make some improvements of the buffer insertion technology of [6] to get better skew results and satisfy the signal polarity constraints of the registers.…”

“…The CTS approach in [6] is adopted to utilize the toplevel clock tree. We make some improvements of the buffer insertion technology of [6] to get better skew results and satisfy the signal polarity constraints of the registers. Finally, the skew optimization algorithm in the third stage reduces the global skew of the whole clock tree below single picoseconds.…”

“…Cheon et al indicated that most of the clock tree capacitance (about 80%) is at the leaf level, which includes all the registers and the wires connecting them and the driving buffers [18]. We made a simple statistic of the clock tree capacitance on the eight ISPD'10 benchmark circuits with the CTS method in [6]. The statistical result shows that buffer capacitance is the major contributor towards the total capacitance of the clock tree (buffer: 58%, wire: 28%, register: 14%).…”

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

“…Table1 Wirelength analysis CKT Traditional Clustering DLWUC 1 23 18 2 25 21 3 26 20 4 26 23 5 21 19 6 20 15 7 19 13 8 17 14 9 21 17 10 15 11 Table 2 Channel width analysis CKT Traditional Clustering DLWUC 1 78 73 2 82 77 3 85 78 4 85 81 5 74 68 6 73 70 7 70 64 8 68 64 9 74 69 10 62 58 The circuits CKT1-CKT6 are created using the ISCAS'89 to validate the number of buffers requirement (Power Mode Aware Buffers (PMAB), Clock Buffers (CKB) and Delay Buffers(DLB)) [3]. The ISPD 2010 benchmark circuits used to validate the effectiveness of proposed algorithm over the existing obstacle avoiding [30], clustering-based Clock Tree Synthesis (CTS) models [28,29] . The comparative analysis shows that the proposed algorithm efficiently achieves the reduction in wirelength, skew and power consumption effectively.…”

Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes

“…ISPD '13, March 24-27, 2013, Stateline, Nevada, USA. skew and slew constraints with an appropriate safety margin [27]. Buffers inserted in the clock network consume a large amount of power and it is necessary to keep the increase in power consumption of the network as small as possible, while maintaining low skew.…”