On-Chip Property Verification Using Assertion Processors

Nacif, José Augusto M.; Coelho, Carlyle Mendes; Foster, Harry; Paula, Flavio M. De; Mota, Edjair; Mota, Márcia Roberta Falcão; Fernandes, A.O.

doi:10.1007/0-387-33403-3_7

Cited by 5 publications

(5 citation statements)

References 16 publications

(13 reference statements)

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“…Although using similar principles to our work achieving RTL-based online design validation, the error information is stored as part of a passive monitoring approach, and unlike our work, it provides no reactive responses to errors. Other assertion-based verification issues are discussed in [3] and [4]. Abramovici et al [5] introduce a distributed reconfigurable fabric inserted at RTL which provides a debug platform that can be configured and operated post-silicon via the JTAG port.…”

Section: Related Researchmentioning

confidence: 99%

Online monitoring of FPGA-based co-processing engines embedded in dependable workstations

Bartzoudis

McDonald-Maier

2007

13th IEEE International on-Line Testing Symposium (IOLTS 2007)

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An assertion-based monitoring system was implemented to enforce the operation of a FPGA coprocessing engine, which is part of a dependable workstation. The monitor was built in VHDL using simple state machines. Concurrent error detection is an important aspect in dependable workstations helping to prevent the propagation of errors within the system. The functionality of the implemented monitoring component does not interfere with the performance of the workstation and ensures high system availability. The monitor checks for PCI protocol and application errors based on the forensic analysis of a dependable workstation with FPGAbased co-processing support.

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Section: Related Researchmentioning

confidence: 99%

Online monitoring of FPGA-based co-processing engines embedded in dependable workstations

Bartzoudis

McDonald-Maier

2007

13th IEEE International on-Line Testing Symposium (IOLTS 2007)

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“…A notable work is "backspace" [6], it uses SAT-solving techniques to provide an execution trace to a crashed post-silicon state, thus facilitating off-line debugging. Several approaches [3,8,12] integrate formal specifications into post-silicon checking of hardware by observing its execution trace. In [14], hardware monitors are introduced to ameliorate observability requirements on silicon.…”

Section: Related Workmentioning

confidence: 99%

Post-silicon conformance checking with virtual prototypes

Xie

Cong

2013

Proceedings of the 50th Annual Design Automation Conference

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Virtual prototypes are increasingly used in device/driver co-development and co-validation to enable early driver development and reduce product time-to-market. However, drivers developed over virtual prototypes often do not work readily on silicon devices, since silicon devices often do not conform to virtual prototypes. Therefore, it is important to detect the inconsistences between silicon devices and virtual prototypes.We present an approach to post-silicon conformance checking of a hardware device with its virtual prototype, i.e., a virtual device. The conformance between the silicon and virtual devices is defined over their interface states. This approach symbolically executes the virtual device with the same driver request sequence to the silicon device, and checks if the interface states of the silicon and virtual devices are consistent. Inconsistencies detected indicate potential errors in either the silicon device or the virtual device. We have evaluated our approach on three network adapters and their virtual devices, and found 15 inconsistencies exposing 15 real bugs in total from the silicon and virtual devices. The results demonstrate that our approach is useful and efficient in facilitating device/driver covalidation at the post-silicon stage.

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“…Several approaches [4], [5], [6] integrate assertions into postsilicon checking of hardware by observing its execution trace. In [7], [8], hardware monitors are introduced to ameliorate observability requirements on silicon.…”

Section: ) Memory Usagesmentioning

confidence: 99%

Optimizing post-silicon conformance checking

Cong

Xie

2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

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Abstract-Virtual prototypes of hardware devices, a.k.a, virtual devices, are increasingly used to enable early software development before silicon prototypes/devices are available. In previous work, we presented a post-silicon conformance checking approach to detecting interface state inconsistencies between a silicon device and its virtual device. In this paper, we present an optimization, adaptive concretization, to reduce the overhead incurred by symbolic execution, a key technique used in our conformance checking approach. We have evaluated our optimized approach on three Ethernet adapters and their virtual devices. The results demonstrate that it is effective and efficient: 21 inconsistencies are discovered and time usages are reduced by an order of magnitude, comparing to the previous approach.

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On-Chip Property Verification Using Assertion Processors

Cited by 5 publications

References 16 publications

Online monitoring of FPGA-based co-processing engines embedded in dependable workstations

Online monitoring of FPGA-based co-processing engines embedded in dependable workstations

Post-silicon conformance checking with virtual prototypes

Optimizing post-silicon conformance checking

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