On-chip thermal gradient analysis and temperature flattening for SoC design

Satō, Takashi; Ichimiya, Junji; Ono, Nobuto; Hachiya, Kotaro; Hashimoto, Masanori

doi:10.1109/aspdac.2005.1466526

Cited by 14 publications

(16 citation statements)

References 11 publications

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“…Local chip temperature variations (also called intra-die temperature variations) can also result in communication errors between units with a large temperature differential. Intra-die temperature variations exceeding 50°C have been reported [30], as shown by the thermal map in Figure 1.6, which shows the temperature gradient between a microprocessor core and an on-chip cache. Adaptive systems with temperature sensors ensure functionality over this wide range of conditions by adjusting cooling systems, supply voltage and/or operating frequency [31][32] [33].…”

Section: Global and Local Temperature Variationmentioning

confidence: 98%

Managing Temperature Effects in Nanoscale Adaptive Systems

Wolpert

Ampadu

2012

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Section: Global and Local Temperature Variationmentioning

confidence: 98%

Managing Temperature Effects in Nanoscale Adaptive Systems

Wolpert

Ampadu

2012

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“…Moreover, it has been demonstrated that large temperature variations cause low reliability and they also have a negative effect on leakage [13]. Thermal balancing does not come as a side effect of energy and load balancing; thus, thermal management and balancing policies are needed [12,5]. Although task and thread migration have been proposed to prevent thermal runaway and to achieve thermal balancing in multithreaded architectures [3,5], Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.…”

Section: Introductionmentioning

confidence: 99%

Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures

Mulas

Pittau

Buttu

et al. 2008

2008 Design, Automation and Test in Europe

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As feature sizes decrease, power dissipation and heat generation density exponentially increase. Thus, temperature gradients in Multiprocessor Systems on Chip (MPSoCs) can seriously impact system performance and reliability. Thermal balancing policies based on task migration have been proposed to modulate power distribution between processing cores to achieve temperature flattening. However, in the context of MPSoC for multimedia streaming computing, where timeliness is critical, the impact of migration on quality of service must be carefully analyzed. In this paper we present the design and implementation of a lightweight thermal balancing policy that reduces on-chip temperature gradients via task migration. This policy exploits run-time temperature and load information to balance the chip temperature. Moreover, we assess the effectiveness of the proposed policy for streaming computing architectures using a cycle-accurate thermal-aware emulation infrastructure. Our results using a real-life software defined radio multitask benchmark show that our policy achieves thermal balancing while keeping migration costs bounded.

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“…However, performing thermally-aware and performance efficient mapping of the workload on the MPSoC is a non-trivial problem. In addition, temperature variations as high as 50ºC across the die are reported in modern microprocessors [16], [34]. Spatial thermal variations are typically larger in heterogeneous MPSoCs due to the intrinsic disparity in power densities across the chip.…”

Section: Introductionmentioning

confidence: 99%

Hybrid dynamic energy and thermal management in heterogeneous embedded multiprocessor SoCs

Sharifi¹,

Coskun²,

Rosing³

2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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ABSTRACT-Heterogeneous multiprocessor system-on-chips (MPSoCs) which consist of cores with various power and performance characteristics can customize their configuration to achieve higher performance per Watt. On the other hand, inherent imbalance in power densities across MPSoCs leads to non-uniform temperature distributions, which affect performance and reliability adversely. In addition, managing temperature might result in conflicting decisions with achieving higher energy efficiency. In this work, we propose a joint thermal and energy management technique specifically designed for heterogeneous MPSoCs. Our technique identifies the performance demands of the current workload. By utilizing job scheduling and voltage/frequency scaling dynamically, we meet the desired performance while minimizing the energy consumption and the thermal imbalance. In comparison to performance-aware policies such as load balancing, our technique simultaneously reduces the thermal hot spots, temperature gradients, and energy consumption significantly.

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On-chip thermal gradient analysis and temperature flattening for SoC design

Cited by 14 publications

References 11 publications

Managing Temperature Effects in Nanoscale Adaptive Systems

Managing Temperature Effects in Nanoscale Adaptive Systems

Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures

Hybrid dynamic energy and thermal management in heterogeneous embedded multiprocessor SoCs

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