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In this paper, we propose a methodology for calculating on-chip temperature gradient and leakage power distributions. It considers the interdependence between leakage power and local temperature using a general circuit simulator as a differential equation solver. The proposed methodology can be utilized in the early stages of the design cycle as well as in the final verification phase. Simulation results proved that consideration of the temperature dependence of the leakage power is critically important for achieving reliable physical designs since the conventional temperature analysis that ignores the interdependence underestimates leakage power considerably and may overlook potential thermal runaway.

-In recent deep submicron VLSI design, signal integrity (SI) and power-ground integrity (PGI) have become very important to design in a short time. As a solution, we propose DEPOGIT, which is a new dense power-ground interconnect architecture that realizes more robust physical design integrity. This architecture is a method of running both the power and ground wires adjacent to the signal wires. This provides not only the general shielding effect but also explicit decoupling capacitance (decap) by means of the wires. Using this architecture also guarantees regularity, thus reducing manufacturing variations in interconnects.As a result of quantitative analysis performed using 90 nm technology node, we demonstrate that high-quality decap of over 50 nF in a 10 mm square chip can be obtained, the resistive IR-drop can be less than 20% of that of a conventional power grid, transient peak noise can be reduced by about 80%, and the inductive crosstalk effect of the signal wire can be greatly reduced.

The difference between FPD and LSIWe describe the main difference in terms of design between FPD and LSI. Verification technique.In LCD panel design made of amorphous silicon for large-screen televisions does not necessarily have the schematic for the panel. As the most of the panel layout consists of pixel arrays and the connections to the drivers, the circuit information is not required. For this reason, the layout can be designed without preparing a schematic. And a design method of generating a new product by modifying the existing data, such as changing the size of the transistor is very common. In this case, to verify the correctness, they will compare the data between pre and post layout. By such reasons, the FPD design requires some special validation functions which are different from semiconductor design. Design of mask (reticle).Compare the semiconductor and FPD mask, the mask of FPD covers a huge area. For example, 100 inches large TV panels can not be exposed by one shot. Therefore, a large TV panels are exposed one by one which are divided into several areas. To expose the panel by the selected area, we must first split the data. Many processes are required to achieve the desired performance as a high-definition television panels. We developed a CAD system which enables to exposure the divided area and verify function to meet the FPD design. In this paper, we explain the specialized verification technology for panel layout, reticle and glass of FPD which enable to reduce the re-spin and design TAT. Fig 1. Any angle wirings