On designing sub-70-nm semiconductor materials and processes

Zhirnov, V.V.; Cavin, Ralph K.; Herr, Daniel J. C.; Wooldridge, Theresa A.

doi:10.1109/66.999587

Cited by 12 publications

(9 citation statements)

References 33 publications

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“…From the analysis of the STM image we calculate an average height difference from peak to valley of ~ 1 nm (which corresponds to ~7 atomic steps) and a root mean square surface roughness ~ 0.95 Å. We observe randomly distributed small mounds that appear as bright features in figure 1(a), with a typical area of ~ 3×3 nm 2 and an apparent height of ~5 Å, as reported previously for Ge(001) surfaces prepared with different methods [25,26]. The exact origin of these features will be the subject of a future detailed STS study.…”

Section: Resultsmentioning

confidence: 96%

“…Electronic device miniaturization to and beyond the 16 nm node requires technological progress other than standard scaling of silicon (Si) complementary metal-oxide-semiconductor (CMOS) technology [1]. This includes replacing Si in transistors with alternative high-mobility channel materials and developing technologies capable of miniaturizing devices at the atomic-scale, where atomically abrupt dopant profiles and interfaces are required [2].…”

Section: Introductionmentioning

confidence: 99%

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Atomic-scale patterning of hydrogen terminated Ge(001) by scanning tunneling microscopy

et al. 2009

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In this paper we demonstrate atomic-scale lithography on hydrogen terminated Ge(001). The lithographic patterns were obtained by selectively desorbing hydrogen atoms from a H resist layer adsorbed on a clean, atomically flat Ge(001) surface with a scanning tunneling microscope tip operating in ultra-high vacuum. The influence of the tip-to-sample bias on the lithographic process have been investigated. Lithographic patterns with feature-sizes from 200 to 1.8 nm have been achieved by varying the tip-to-sample bias. These results open up the possibility of a scanning-probe lithography approach to the fabrication of future atomic-scale devices in germanium.

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Section: Resultsmentioning

confidence: 96%

Section: Introductionmentioning

confidence: 99%

Atomic-scale patterning of hydrogen terminated Ge(001) by scanning tunneling microscopy

et al. 2009

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“…Ge-based atomic scale-devices are particularly interesting since the electronic device miniaturization to and beyond the 16-nm-node foresees the replacement of Si channel in transistors with higher mobility materials 4,5 and requires, ultimately, the development of technologies capable of miniaturizing devices at the atomic-scale. 6 Any design of future atomic-scale Ge devices -such as ultra-shallow abrupt junctions, ballistic transistors or quantum coherent devices -requires a detailed knowledge of the carrier transport properties in the starting two-dimensional (2D) Ge:P -doped layer as a function of the fabrication process parameters. Previous studies on Si:P -doped layers have highlighted the crucial role of the temperature at which the encapsulation layer is grown (T g ) in determining the spatial confinement and electronic transport properties of dopants due to the interplay between epi-layer crystal quality and dopant segregation.…”

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confidence: 99%

Influence of encapsulation temperature on Ge:Pδ-doped layers

2009

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We present a systematic study of the influence of the encapsulation temperature on dopant confinement and electrical properties of Ge:P ␦-doped layers. For increasing growth temperature we observe an enhancement of the electrical properties accompanied by an increased segregation of the phosphorous donors, resulting in a slight broadening of the ␦ layer. We demonstrate that a step-flow growth achieved at ϳ530°C provides the best compromise between high crystal quality and minimal dopant redistribution, with an electron mobility ϳ128 cm 2 / Vs at a carrier density 1.3ϫ 10 14 cm −2 , and a 4.2 K phase coherence length of ϳ180 nm.The recent demonstration of phosphorus in germanium ͑Ge:P͒ ␦-doped layers 1 and of atomic-scale scanning tunneling microscope ͑STM͒ hydrogen lithography on Ge͑001͒ ͑Ref. 2͒ has opened the possibility of an ultrahigh vacuum ͑UHV͒ STM approach to the fabrication of atomic-scale devices in Ge analogous to the one developed for atomic-scale devices in silicon. 3 This approach consists of using an STM to create a laterally patterned dopant ␦ layer which is then encapsulated under a homoepitaxial layer deposited by molecular beam epitaxy. The spatially defined ␦ layer is obtained by selective adsorption and incorporation of dopants on depassivated areas of a hydrogen-terminated Ge͑001͒ surface in which H atoms have been locally removed by an STM tip. Ge-based atomic scale devices are particularly interesting since the electronic device miniaturization to and beyond the 16-nm-node foresees the replacement of Si channel in transistors with higher mobility materials 4,5 and requires, ultimately, the development of technologies capable of miniaturizing devices at the atomic scale. 6 Any design of future atomic-scale Ge devices-such as ultrashallow abrupt junctions, ballistic transistors or quantum coherent devices-requires detailed knowledge of the carrier transport properties in the starting two-dimensional ͑2D͒ Ge:P ␦-doped layer as a function of the fabrication process parameters. Previous studies on Si:P ␦-doped layers have highlighted the crucial role of the temperature at which the encapsulation layer is grown ͑T g ͒ in determining the spatial confinement and electronic transport properties of dopants due to the interplay between epilayer crystal quality and dopant segregation. 7,8 Ideally one would need to carefully control the process thermal budget to find the maximum temperature that guarantees encapsulation of dopants in a highquality crystal while minimizing dopant redistribution. In silicon this has proven to be a difficult task: Si:P ␦ layers are typically encapsulated at low temperatures ͑ϳ250°C͒ to avoid P segregation at the expense of a rougher surface. 7-9 In this paper, instead, we demonstrate that for Ge:P ␦-doped layers a compromise between high crystal quality and minimal dopant redistribution is possible at a growth temperature ϳ530°C, sufficient to achieve a high-quality step-flow Ge growth. To this end we present a systematic study of the effect of Ge encapsulation temperatur...

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“…In silicon, multiple dÀlayers have also been grown to investigate the formation of ultra-shallow junction layers [10]. If combined with scanning tunneling microscopy (STM) dÀdoping can be used to fabricate ultra-shallow junctions with atomically abrupt doping profiles, allowing the controlled positioning of dopants in all three spatial dimensions [11]. This combined approach provides a route towards the fabrication of novel device structures such as atomic-scale dÀFETs.…”

Section: Introductionmentioning

confidence: 99%