On diagnosing path delay faults in an at-speed environment

Tekumalla, R.C.; Venkataraman, S.; Ghosh-Dastidar, J.

doi:10.1109/vts.2001.923414

Cited by 12 publications

(2 citation statements)

References 22 publications

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“…People have been using at-speed scan test patterns to identify delay defects during product silicon debug [11][12][13][14][15][16][17][18][19][20][21][22]. Path delay fault model has been used in previous works to diagnose delay defects [12] [13] [14] [15], but the diagnostic resolution for path delay faults hasn't achieved an acceptable level, especially when there are multiple faults in the circuit under diagnosis.…”

Section: Review Of Previous Workmentioning

confidence: 99%

Speed-Path Debug Using At-Speed Scan Test Patterns

Guo

Cheng

Tsai

2009

2009 14th IEEE European Test Symposium

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Speed path debug is a critical step to improve the performance of high performance VLSI designs. The purpose of speed path debug is to identify the performance limiting paths and fix them in the next product stepping so that the chip can run at a higher clock frequency. This paper investigates speed path debug techniques using atspeed scan test patterns. For each failing scan cell, the failing paths are identified based on structural analysis of logic simulation values. We further propose two metrics to rank the identified speed paths based on logic value analysis and based on timing information calculated for the failing pattern. Experimental results show the effectiveness of the proposed speed path debug technique.

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Section: Review Of Previous Workmentioning

confidence: 99%

Speed-Path Debug Using At-Speed Scan Test Patterns

Guo

Cheng

Tsai

2009

2009 14th IEEE European Test Symposium

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“…To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. with single delay faults [7,10]. Dastidar and Touba [3] describe a diagnostic algorithm based on critical path-tracing under six value algebra.…”

Section: Introductionmentioning

confidence: 99%

Diagnosing multiple transition faults in the absence of timing information

Liu¹,

Abadir²,

Veneris

et al. 2005

Proceedings of the 15th ACM Great Lakes Symposium on VLSI

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As timing requirements in today's advanced VLSI designs become more aggressive, the need for automated tools to diagnose timing failures increases. This work presents two such algorithms capable of diagnosing multiple delay faults. One method uses multiple transition fault models and the other reasons with ternary logic values, thus achieving modelindependent diagnosis. Experiments are conducted on IS-CAS'85 combinational and full-scan version of ISCAS'89 sequential circuits corrupted with multiple transition faults. The performance of both algorithms are evaluated and compared. The results show good efficiency and diagnostic resolution.

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A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities

Chen

Liou

2009

2009 Asian Test Symposium

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On diagnosing path delay faults in an at-speed environment

Cited by 12 publications

References 22 publications

Speed-Path Debug Using At-Speed Scan Test Patterns

Speed-Path Debug Using At-Speed Scan Test Patterns

Diagnosing multiple transition faults in the absence of timing information

A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities

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