Speed-Path Debug Using At-Speed Scan Test Patterns

Abstract

Speed path debug is a critical step to improve the performance of high performance VLSI designs. The purpose of speed path debug is to identify the performance limiting paths and fix them in the next product stepping so that the chip can run at a higher clock frequency. This paper investigates speed path debug techniques using atspeed scan test patterns. For each failing scan cell, the failing paths are identified based on structural analysis of logic simulation values. We further propose two metrics to rank the identified speed paths based on logic value analysis and based on timing information calculated for the failing pattern. Experimental results show the effectiveness of the proposed speed path debug technique.