2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)
DOI: 10.1109/asap.2005.47
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On Estimations for Compiling Software to FPGA-based Systems

Abstract: This paper presents recent advances in a compiler infrastructure to map algorithms described in a Java subset to FPGA-based platforms. We explain how delays and resources are estimated to guide the compiler through scheduling and temporal partitioning. The compiler supports complex analytical models to estimate resources and delays for each functional unit. The paper presents experimental results for a number of benchmarks. Those results also arrise a question when performing temporal partitioning: shall we tr… Show more

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Cited by 5 publications
(2 citation statements)
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“…Based on this, one can achieve comparable performance for the implementations obtained by mapping well-known digital signal processing algorithms (most regular) into this layer (i.e., the one provided by the CGRA structures on top of the FPGA resources) when compared to implementations obtained by high-level synthesis [18]. Note that the application-specific architectures generated by high-level synthesis tools, at a first glance would be expected to achieve higher performance, may suffer from non-optimal P&R and from long interconnections and irregular structures [19].…”
Section: Introductionmentioning
confidence: 99%
“…Based on this, one can achieve comparable performance for the implementations obtained by mapping well-known digital signal processing algorithms (most regular) into this layer (i.e., the one provided by the CGRA structures on top of the FPGA resources) when compared to implementations obtained by high-level synthesis [18]. Note that the application-specific architectures generated by high-level synthesis tools, at a first glance would be expected to achieve higher performance, may suffer from non-optimal P&R and from long interconnections and irregular structures [19].…”
Section: Introductionmentioning
confidence: 99%
“…A methodology to estimate area and time on FPGA for applications written in Java is proposed in [110]. Bilavarn et al performs area, time and power estimation by transforming C functions to hierarchical control data flow graphs [111].…”
Section: High Level Synthesis (Hls) Based Estimationmentioning
confidence: 99%