2001
DOI: 10.1109/55.902843
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On experimental determination of carrier velocity in deeply scaled NMOS: how close to the thermal limit?

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Cited by 150 publications
(85 citation statements)
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“…The gate insulator in our current devices is un-optimized and thicker than the channel length. It will be feasible to integrate high κ dielectrics such as ZrO 2 9 into SWNT-contacted molecular FETs to afford ~10-fold increase in C G and therefore further enhance the electrostatic gate control. With quasi-1D contacts, gate scaling could allow for organic transistors approaching the limit of S ~ 60 mV/decade.…”
Section: B Cmentioning
confidence: 99%
“…The gate insulator in our current devices is un-optimized and thicker than the channel length. It will be feasible to integrate high κ dielectrics such as ZrO 2 9 into SWNT-contacted molecular FETs to afford ~10-fold increase in C G and therefore further enhance the electrostatic gate control. With quasi-1D contacts, gate scaling could allow for organic transistors approaching the limit of S ~ 60 mV/decade.…”
Section: B Cmentioning
confidence: 99%
“…To this purpose, in [4] the BR is extracted by comparing the product Q inv v inj with I D , where Q inv is obtained by C/V measurements and v inj is estimated by means of simulations. The method in [1,5], instead, evaluates r directly from the variations of I D and of the threshold voltage V T with temperature.…”
Section: Introductionmentioning
confidence: 99%
“…Consider first the charge at the virtual source. It can be estimated from experiment C−V (long channel) from [38,39] …”
Section: Charge Control In a Nanoscale Hemtmentioning
confidence: 99%