We analyze a modern-day 65nm MOSFET technology to determine its electrical characteristics and intrinsic ballistic efficiency. Using that information, we then predict the performance of similar devices comprised of different materials, such as high-k gate dielectrics and III-V channel materials. The effects of series resistance are considered. Comparisons are made between the performance of these hypothetical devices and future generations of devices from the ITRS roadmap, including double-gate MOSFETs. We conclude that a Si channel device with a high-k gate dielectric and metal gate will outperform III-V channel materials for conventional CMOS applications, but will still not suffice in achieving long-term ITRS goals.Mater. Res. Soc. Symp. Proc. Vol. 958

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The device physics and technology issues for III-V transistors are examined from a simulation perspective. To examine device physics, an InGaAs HEMT structure similar to those being explored experimentally is analyzed. The physics of this device is explored using detailed, quantum mechanical simulations based on the non-equilibrium Green's function formalism. In this chapter, we: (1) elucidate the essential physics of III-V HEMTs, (2) identify key technology challenges that need to be addressed, and (3) estimate the expected performance advantage for III-V transistors. IntroductionDriven by tremendous advances in lithography, the semiconductor industry has followed Moore's law by shrinking transistor dimensions continuously for the last 40 years. The big challenge going forward is that continued scaling of planar, silicon, CMOS transistors will be more and more difficult because of both fundamental limitations and practical considerations as the transistor dimensions approach ten nanometers. The issues at small gate lengths are many fold. First, transistor scaling increases the number of gates on a chip and the operating frequency. To prevent the chip from overheating, the power dissipation should be limited, which requires lowering the power supply voltage while maintaining the ability to deliver high oncurrents for each new generation of technology. Secondly, the drain bias decreases the energy barrier height between the source and channel in a transistor due to 2D electrostatics. Degraded short channel effects become more significant as the gate length gets shorter, and the increased off-state leakage has pushed the standby power to its practical limit. Thirdly, the accompanying scaled oxide thickness provides better gate control of the channel potential, but this inevitably increases S. Oktyabrsky, P. D. Ye (eds.), Fundamentals of III-V Semiconductor MOSFETs,

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