On nanoelectronic architectural challenges and solutions

Beiu, Valeriu; Rückert, Ulrich; Roy, Soumyajit; Nyathi, J.

doi:10.1109/nano.2004.1392441

Cited by 26 publications

(9 citation statements)

References 2 publications

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“…The use of AVLG Technique decreases the power consumption through an Half Subtractor. Therefore, this approach is useful in lowering the final value of the power consumption [13]. This technique makes use of supply voltage.…”

Section: Half Subtractor Using Avlgmentioning

confidence: 99%

Reduction of Leakage Power in Half- Subtractor using AVL Technique based on 45nm CMOS Technology

SinghNarwariya¹,

Akashe²

2015

IJCA

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The analytical paper of arithmetic circuits plays an important role in designing of any VLSI system. Subtractor is one of them. Half Subtractor is being designed using Adaptive Voltage Level (AVL) techniques. This design consumed less power as compare to conventional design. We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level at supply) in which supply potential is increased. This paper represents how to control power using AVL techniques. The AVL technique based Half Subtractor compared to conventional design that based on power consumption, propagation delay, speed and layout area is more preferred. Power consumption of the projected cell is measured and compared. The result shows that there is a significant reduction in power consumption for this proposed cell with the AVL technique. This styal is much useful in designing the system that consumed less power. The circuit is simulated on Cadence tools in 45 nanometer CMOS technology.

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Section: Half Subtractor Using Avlgmentioning

confidence: 99%

Reduction of Leakage Power in Half- Subtractor using AVL Technique based on 45nm CMOS Technology

SinghNarwariya¹,

Akashe²

2015

IJCA

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“…With device geometries scaling below the 65 nm range, the available reliability margins are drastically being reduced [2], [3]. From the chip designers' perspective, reliability manifests itself more and more as time-dependent uncertainties in electrical parameters.…”

Section: Introductionmentioning

confidence: 99%

Why Nano-DSP Will be Fan-In Constrained

Ibrahim

Beiu

Lazarova-Molnar

2007

2007 IEEE International Conference on Signal Processing and Communications

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This paper studies for the first time the performance of von-Neumann multiplexing (vN-MUX) when stuck at fault model is considered. In this study, vN-MUX is applied to majority (MAJ) gates of small fan-ins (A = 3, 5, 7, and 9), and respectively the corresponding redundancy factors (R= 6, 10, 14, and 18). This study is extremely important for a deeper understanding of vN-MUX, especially when considering the unreliable behavior of future nano-devices. The analysis confirms and enhances on well-known theoretical results, and is exact as being obtained using Bayesian network. Finally, the extension to device level will allow us to characterize vN-MUX with respect device failures for the first time ever. The results are very timely and are explaining a strange (non-linear) behavior of vN-MUX that was first reported two years ago (based on extensive Monte Carlo simulations).

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“…Single electron technology (SET) is one of the emerging nano-technologies distinguished not only by very small device sizes, but also by its ultra-low power dissipation [3]. Still, reliability is a crucial issue-for SET in particular, and all nano devices in general-so a deeper understanding of the reliability-redundancy (area) tradeoffs needs a lot of effort and investigations [4].…”

Section: Introductionmentioning

confidence: 99%

“…The well-known approach for developing reliable architectures in the face of uncertainties (both defects and transient faults) is to incorporate spatial and/or temporal redundancy. Many redundancy schemes have been proposed and investigated in the literature, including: modular redundancy, cascaded modular redundancy, multiplexing (MUX, including von Neumann multiplexing [10] and parallel restitution [7]), as well as reconfiguration [3], [4], [11]. We note here that improved reliability is traded off for area and connectivity.…”

Section: Introductionmentioning

confidence: 99%

Gate Failures Effectively Shape Multiplexing

Beiu

Ibrahim

Alkhawwar

et al. 2006

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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This paper investigates the behavior of multiplexing (MUX) schemes in combination with the elementary gates. The two schemes under investigation are majority (MAJ) and NAND MUX. The simulation results presented here are for single-electron technology, but could easily be extended to CMOS. The components of the gates have been subjected only to geometric variations. Firstly, the gates and the two MUX schemes are analyzed theoretically. Secondly, simulations using probability transfer matrices (PTM) allow evaluating both MUX schemes at a redundancy factor R = 6. Finally, the gates are compared in terms of their intrinsic probability of failure (with respect to geometric variations), and the two MUX schemes are weighted against the reliability enhancements they are bringing into the system. By comparing the simulation results from PTM with the ones based on (geometric) variations, this study gives deeper insights into the behavior of MUX schemes, and show that the gates play a major role, strongly affecting MUX systems.

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On nanoelectronic architectural challenges and solutions

Cited by 26 publications

References 2 publications

Reduction of Leakage Power in Half- Subtractor using AVL Technique based on 45nm CMOS Technology

Reduction of Leakage Power in Half- Subtractor using AVL Technique based on 45nm CMOS Technology

Why Nano-DSP Will be Fan-In Constrained

Gate Failures Effectively Shape Multiplexing

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