On Reconfigurable Single-Electron Transistor Arrays Synthesis Using Reordering Techniques

Chiang, Chang-En; Tang, Li-Fu; Wang, Chun-Yao; Huang, Ching-Yi; Chen, Yung-Chih; Datta, Suman; Narayanan, Vijaykrishnan

doi:10.7873/date.2013.362

Cited by 13 publications

(23 citation statements)

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“…We can see that compared to the method in [8], our method saves 51% area on average in terms of the number of hexagons. The average runtime of our algorithm is less than 0.005 second, and the longest runtime of all benchmarks is less than 1.1 seconds, which is a large improvement over the previous method.…”

Section: Resultsmentioning

confidence: 89%

“…A set of MCNC and IWLS 2005 benchmarks [12] were used. Same as the previous methods in [7] and [8], we apply the BDD reordering heuristic CUDD_REORDER_SYMM_SIFT [11] after reading a benchmark; also same as the previous methods, for a multiple-output function, we mapped the function of each primary output (PO) separately onto an SET array. The area of a benchmark is measured by the total numbers of hexagons in the SET arrays for all the POs.…”

Section: Resultsmentioning

confidence: 99%

“…Table I shows the experimental results. We show the number of hexagons, total runtime, and the respective ratios of our proposed algorithm and the algorithm proposed in [8] in Columns 4 to 9.…”

Section: Resultsmentioning

confidence: 99%

“…After obtaining the product terms 10 and 01, the left path is configured for 10, and then the right path is configured for 01. Among all the previous works, [8] provides the best result in terms of the area of the SET array.…”

Section: Related Work and Motivationmentioning

confidence: 96%

“…3 shows an example of mapping an ROBDD (in which the edges connected to the 0-terminal are omitted) to an SET array by our method (Fig. 3b) and by the product term-based method of [8] (Fig. 3c).…”

Section: Related Work and Motivationmentioning

confidence: 99%

See 4 more Smart Citations

BDD-based synthesis of reconfigurable single-electron transistor arrays

Zhao

Liu

Wang

et al. 2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Single-electron transistor (SET) is an ultra-low power device, which has been demonstrated as a promising alternative for CMOS devices in reducing power consumption. A suitable structure for realizing logic function using SET is a binary decision diagram (BDD)-based SET array. Previous works proposed product term-based automated synthesis methods to map a given logic function onto an SET array. In this work, we propose a novel BDD-based synthesis method that exploits the structure similarity between an SET array and a BDD. Our method transforms a BDD of a Boolean function into a planar graph and further maps the graph onto an SET array. Experiment results showed that compared to the state-of-the-art synthesis method, our method saves 51% in area on average and is more than 16 times faster.

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Section: Resultsmentioning

confidence: 89%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Related Work and Motivationmentioning

confidence: 96%

Section: Related Work and Motivationmentioning

confidence: 99%

See 3 more Smart Citations

BDD-based synthesis of reconfigurable single-electron transistor arrays

Zhao

Liu

Wang

et al. 2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Self Cite

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Automatic verification of single‐electron transistor arrays based on multiway decision graphs

Abed

Ahmad

Shayeji

et al. 2017

IET Circuits, Devices & Systems

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The single-electron transistor (SET) is considered as a promising alternative to CMOS devices and integrated circuits due to its ultra-low-power consumption. The authors propose an automatic methodology by utilising SET-based multiway decision graph (MDG) for implementing SET architecture. MDG provides a powerful means of abstraction and can be used to manipulate a certain type of first-order logic formula called directed formula (DF). An automatic tool has been developed that is capable of transferring the SET array into MDG DF to generate all paths of all possible reachable states, drawing an abstract diamond-shaped network for the SET array, producing a reduced DF generated by the MDG tool and converting the reduced DF into a conjunctive normal form formula. Then, the authors use the satisfiability approach as a verification engine to verify the correctness of these conversions. The method is tested and verified using MCNC benchmarks. The results outperform approaches based on binary decision diagrams in terms of verification time, number of clauses and variables.

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