On sensor image compression

Aizawa, Kiyoharu; Ohno, Hiroshi; Egi, Y.; Hamamoto, Takayuki; Hatori, Mitsutoshi; Maruyama, Hirotaka; Yamazaki, Junichi

doi:10.1109/76.585933

Cited by 32 publications

(7 citation statements)

References 7 publications

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“…In fact, as early as in 1997, imagers integrated with parallel inarray processing circuit were being reported in [21,70]. In the proposed work, a computational image sensor explores the parallel nature of image signal by integrating conditional replenishment algorithm, a pixel-level video compression schemes, which removes temporal redundancy of pixels between consecutive frames.…”

Section: Aps Array With Focal-plane Compression Processormentioning

confidence: 99%

“…CMOS technology enables the integration of image sensing and image processing, making the CMOS image sensor the optimum solution to improve the performance of the overall system. In the last several decades, image sensors integrating different on-chip compression algorithms, such as predictive coding [18], wavelet-based image processing [19], DCT-based image processing [20], conditional replenishment [21], SPIHT algorithm [22], and FBAR and QTD processing [23] have been developed. A simplest way to design such a system is to implement different functions using sperate circuit units, such as image-sensing unit and image-compression processing unit.…”

Section: Introductionmentioning

confidence: 99%

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CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

Zhang

Bermak

2010

Journal of Sensors

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Demand for high-resolution, low-power sensing devices with integrated image processing capabilities, especially compression capability, is increasing. CMOS technology enables the integration of image sensing and image processing, making it possible to improve the overall system performance. This paper reviews the current state of the art in CMOS image sensors featuring on-chip image compression. Firstly, typical sensing systems consisting of separate image-capturing unit and image-compression processing unit are reviewed, followed by systems that integrate focal-plane compression. The paper also provides a thorough review of a new design paradigm, in which image compression is performed during the image-capture phase prior to storage, referred to as compressive acquisition. High-performance sensor systems reported in recent years are also introduced. Performance analysis and comparison of the reported designs using different design paradigm are presented at the end.

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Section: Aps Array With Focal-plane Compression Processormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

Zhang

Bermak

2010

Journal of Sensors

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“…In addition, advanced smart sensors seek to perform processing in sensors themselves, primarily to reduce the amount of network data traffic [3]. Sensors which have added intelligence, are able to perform tasks such as conversions, monitor machinery for wear, perform image compression, monitor neighborhoods for real-time pollen count, or even spy plane applications, as discussed in [1][11] [21].…”

Section: Related Workmentioning

confidence: 99%

First results with eBlocks

Cotterell

Vahid

Najjar

et al. 2003

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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We describe our first efforts to develop a set of off-the-shelf hardware components that ordinary people could connect to build a simple but useful class of embedded systems. The class of systems, which we call monitor/control systems, is composed primarily of sensors -light, motion, sound, contact, and other types -and output devices -light-emitting diodes, beeping speakers, or even electric relays that control electric appliances like lamps. For example, one monitor/control system would detect if a house's garage door was open at night, and would blink an LED inside the house to alert the homeowner of this normally undesirable situation. Today, configuring even the most basic monitor/control system requires knowledge of electronics and programming. We seek to create a set of building blocks, which we call eBlocks, that would enable someone with no knowledge of electronics or programming to be able to build simple but useful monitor/control systems. We are creating eBlocks largely by incorporating intelligence into previously dumb sensors and output devices, and by developing a set of standards and methods that enable eBlocks to work together seamlessly when connected. eBlocks have only recently become possible due to the extremely low cost, low power, and small size of embedded microprocessors. We describe our first results of creating a basic class of eBlocks, Boolean eBlocks, that from a user's perspective transmit or receive only "yes" or "no" signals. We discuss the internal eBlock design, eBlock system design issues and decisions, and several eBlock-based systems designed by ourselves and by undergraduate students.

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“…Fixed pattern noise is also reduced in this design using a clever feedback technique. Aizawa et al 30 describes a pixel circuit which can be used to perform video compression using conditional replenishment. A pixel is updated or replenished only if its current value differs substantially from its previously stored value.…”

Section: Analog Pixel Processingmentioning

confidence: 99%

<title>Pixel-level processing: why, what, and how?</title>

1999

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Pixel level processing promises many significant advantages including high SNR, low power, and the ability to adapt image capture and processing to different environments by processing signals during integration. However, the severe limitation on pixel size has precluded its mainstream use. In this paper we argue that CMOS technology scaling will make pixel level processing increasingly popular. Since pixel size is limited primarily by optical and light collection considerations, as CMOS technology scales, an increasing number of transistors can be integrated at the pixel. We first demonstrate that our argument is supported by the evolution of CMOS image sensors from PPS to APS. We then briefly survey existing work on analog pixel level processing and pixel level ADC. We classify analog processing into intrapixel and interpixel. Intrapixel processing is mainly used to improve sensor performance, while interpixel processing is used to perform early vision processing. We briefly describe the operation and architecture of our recently developed pixel level MCBS ADC. Finally we discuss future directions in pixel level processing. We argue that interpixel analog processing is not likely to become mainstream even for computational sensors due to the poor scaling of analog compared to digital circuits. We argue that pixel level A/D conversion will become increasingly popular since it minimizes analog processing, and requires only simple and imprecise circuits to implement. We then discuss the inclusion of digital memory and interpixel digital processing in future technologies to implement programmable digital pixel sensors.

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On sensor image compression

Cited by 32 publications

References 7 publications

CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

First results with eBlocks

<title>Pixel-level processing: why, what, and how?</title>

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