On the Advantages of Serial Architectures for Low-Power Reliable Computations

Abstract

This paper explores low-power reliable microarchitectures for addition. Power, speed, and reliability (both defect-and fault-tolerance) are important metrics of system design, spanning device, gate, block, and architectural levels. The analysis considers the low power needs of future systems at supply voltages comparable to threshold voltages (V th ). Theoretical analysis and simulations show a decline of the speed advantages of parallel adders when considering wire delays. These evaluations suggest that serial adders might do better for (ultra) low-power operation, with redundancy for enhancing reliability. We analyze 32-bit multiplexed serial adders. The robustness when using output-wired mirrored adder (majority) gates is shown under faulty conditions. Simulations (at 180 nm, 120 nm, and 70 nm) identify the supply voltages where the power-delay-and energy-delay-products are minimized. These show that redundant serial adders are not only low-power and reliable, but can trade speed for power in a wide range (by varying V DD both above and below V th ).

Femto Joule Switching for Nano Electronics

“…These studies have been on standard CMOS, pseudo-nMOS, and outputwired-inverters [58], [63]- [67]. Based on the ring oscillator simulations at different technology nodes we conclude that the delay reduces with each technology node and we can only expect it to reduce further at lower technology nodes (recent results for the 70 nm node are being reported in [65]- [67]). Table II presents simulation results for three different technology nodes.…”

“…Besides the low speed attribute, another problem with designs in subthreshold is that they are sensitive to variations and noise, hence raising concerns about their reliability. An added bonus of output wired structures is the ease of increasing reliability by simply wiring them in parallel [65]- [67], hence naturally implementing majority multiplexing (a fault tolerant technique) [68], [69]. Such structures also allow for a seamless integration with reconfiguration (a defect tolerant technique), without the need of complex testing [65], [67] (based on the automatic detection of increases in currents).…”