On the Appropriate Handling of Metastable Voltages in FPGAs

Abstract

The signi¯cant process, voltage and temperature (PVT) variations seen with modern technologies make strictly synchronous design ine±cient. Asynchronous design with its°exible timing is a promising alternative, but prototyping is di±cult on the available FPGA platforms which are clock centric and do not provide the required functional primitives like mutual exclusion or Muller C-elements. The solutions proposed in the literature so far work nicely in principle but cannot safely handle metastability issues that are inevitable even at some interfaces in asynchronous designs. In this paper, we propose reliable implementations of the fundamental function blocks required to safely convert potential intermediate voltage levels that result from metastability into late transitions that can be reliably handled in the asynchronous domain. These are high-and low-threshold bu®ers as well as a Schmitt-trigger. We give elaborate background analysis for the proposed circuits and also present the associated routing constraints to make the Schmitt-trigger circuit work properly in spite of the uncertain routing within FPGAs. Furthermore, we propose a procedure for an \in situ reliability assessment" of the speci¯c Schmitt-trigger element under consideration, which also applies to metastability containment with high-or low-threshold bu®ers only. Our proof of concept is based on experimental results for both Xilinx and Altera FPGA platforms.

Measurements of metastability in MUTEX on an FPGA

“…Then, their outputs are inverted to obtain the grant signals as shown in Fig. 1 [11]. In fullcustom design, the two cross-coupled NAND gates can be optimized so that the time delays of feedback paths are as minimal as possible.…”

“…Normally, a filter can be attached to the MUTEX outputs to avoid the metastable signals propagating to the successive circuits. Two inverters with low voltage thresholds are proven as good circuits to filter out the metastability [11]. These filters will keep their outputs unchanged (logic-0) until the MUTEX exactly determines which request wins.…”