On the design of optimal counter-based schemes for test set embedding

State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores

“…Test set embedding techniques require less test data storage than test data compression methods, since they encode the pre-computed test vectors in long pseudorandom sequences generated on-chip. In [8] and [31] the pseudorandom sequences are generated by counters. In [22] an area-demanding reconfigurable interconnection network is presented that achieves a vast reduction of the test data stored on ATE.…”

“…The main drawback of these techniques is their prohibitively long test application time. The multiphase method proposed in [9] has small hardware overhead and generates shorter test sequences than [8], [22] and [31]. An even higher reduction of the test sequence length is achieved in [11] at the expense of a slight increase in test data volume.…”

LFSR Reseeding with Irreducible Polynomials

“…In order to address this issue, many reseeding techniques have been proposed in the literature (see, e.g., [11], [10], [14], [3], [13], [12], [1], [8], [7], [9]). We note that the idea of reseeding applies to non-LFSR TPG mechanisms as well, such as counters and accumulators (see, e.g., [16], [6], [2]), but in this work we are concerned with LFSRs.…”

Deterministic Built-in TPG with Segmented FSMs

“…Another set of methods [28], [19] alter the bits or bit sequences of an on-board PRPG. On the other hand deterministic BIST methods [25], [23], [24], [5], [8], [15], [14], [17], [11], [10], [27] use special PRPGs such as Weighted Random Generators, Galois LFSRs, Cellular Automaton, Counters, and Accumulators to obtain directly the desired DTS.…”