On the Frequency Response and Optimum Designs for Maximum Bandwidth of a Lateral Silicon Photodetector

Das, N. R.; Rakshit, P. C.

doi:10.1109/jlt.2011.2162820

Cited by 6 publications

(1 citation statement)

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“…[27][28][29] Simultaneously, detectors can be designed in a vertical configuration to improve their bandwidths as mentioned above, but a lateral structure is more preferred as it is suitable for integration of the p-i-n PDs with MOSFETs. The interdigitated configuration of lateral p-i-n PDs can be formed on a low-doped Si substrate, 11,18,30,31) which is employed to maximize the depleted regions available for high-speed drift carrier collection. However, it increases the diffusion current from the substrate and the parasitic effects due to the diodes in lateral arrangements.…”

Section: Introductionmentioning

confidence: 99%

Over 10 GHz lateral silicon photodetector fabricated on silicon-on-insulator substrate by CMOS-compatible process

Maekita

Mitsuno

et al. 2015

Jpn. J. Appl. Phys.

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We report a design and implementation of lateral silicon photodetectors fabricated on a silicon-on-insulator (SOI) substrate in a complementary CMOS-compatible process. In addition, we disscuss the structure dependences on the frequency and optimum design for a maximum bandwidth. A standard device fabricated with a 210 nm absorbing layer, a finger width of 1.00 µm, a finger spacing of 1.63 µm, a square detector area of 20 × 20 µm2, and a pad size of 60 × 60 µm2 achieved a bandwidth of 12.6 GHz at a bias voltage of 10 V, with a responsivity of 7.5 mA/W at 850 nm wavelength. A photodetector with the same geometry, which was fabricated with a smaller pad size of 30 × 30 µm2, exhibited a bandwidth of 13.6 GHz.

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