On the jitter requirements of the sampling clock for analog-to-digital converters

Dalt, Nicola Da; Harteneck, M.; Sandner, C.; Wiesbauer, A.

doi:10.1109/tcsi.2002.802353

Cited by 101 publications

(46 citation statements)

References 6 publications

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“…In this section we will derive the sampling clock PLL phase noise profile requirements based on in-band SNR specification of high sampling rate PSDMs under blocking conditions. For the sampling clock phase noise, we follow an analysis similar to [10], which is based on linear approximation of input signal at the sampling instant. Figure 5 shows time domain approximation of the sampling clock inaccuracy on the A/D input.…”

Section: Sampling Clock Phase Noise Impact On Blocking Dynamic Range mentioning

confidence: 99%

“…Equation 10 has several critical points that should be emphasized: (a) as oversampling frequency of the ADC increases, the impact of sampling clock phase noise on received signal decreases, (b) for a multi-tone including in-band blockers, the sampling clock phase noise scales with the blocker power and can 'spill-over' into baseband, reducing blocking dynamic range (BDR). For this analysis we assume a simplified synthesizer single-sided phase noise model of a type I PLL as follows:…”

Section: Sampling Clock Phase Noise Impact On Blocking Dynamic Range mentioning

confidence: 99%

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Design and analysis of a CMOS passive Σ∆ ADC for low power RF transceivers

Chen¹,

Bakkaloglu

Ramaswamy

2008

Analog Integr Circ Sig Process

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Design and analysis of a RD modulator with a passive switched capacitor loop filter is presented. Design steps for optimum loop filter design for quantization noise suppression and thermal noise reduction is outlined. Design specifications for sampling clock phase noise, reference buffer and input buffer settling is analyzed. Presented design has a 2nd-order loop filter and uses only metalmetal capacitors and thin oxide digital transistors with no additional components occupying less than 0.1 mm 2 silicon area in 0.13 lm CMOS digital process. Measurement results show that the ADC achieves 80 dB peak SNR at a 100 kHz integration bandwidth with 1 pJ/sample conversion efficiency. With decimation filter power consumption of 0.22 mW at 104 MHz sampling rate, the ADC consumes only about 1 mA at 1.5 V for each channel.

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Section: Sampling Clock Phase Noise Impact On Blocking Dynamic Range mentioning

confidence: 99%

Section: Sampling Clock Phase Noise Impact On Blocking Dynamic Range mentioning

confidence: 99%

Design and analysis of a CMOS passive Σ∆ ADC for low power RF transceivers

Chen¹,

Bakkaloglu

Ramaswamy

2008

Analog Integr Circ Sig Process

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“…Both assume a sinusoidal signal and zeromean gaussian jitter around fixed "perfect" sampling points. This latter assumption has been found experimentally to be reasonable (Shinagawa, 1990), although the spectrum is not white if a phase-locked loop is used to generate the clock (Da Dalt, 2002), or if the jitter is accumulative (Awad, 1998). The first formula assumes that 1 2 << n c f τ π , where f c is the carrier frequency of the sampled signal, i.e.…”

Section: Aperture Jittermentioning

confidence: 99%

Aperture Jitter Effects in Software Radio GNSS Receivers

Dempster

2004

J. of GPS

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Abstract. Increasingly, software radio techniques are being used in the implementation of communications receivers in general, and GNSS receivers in particular. In such a receiver, the received signal is sampled as close to the receive antenna as possible, and all subsequent processing uses digital signal processing (DSP) techniques. The sampling clock will suffer from phase noise instabilities, leading to a phenomenon known as aperture jitter. This paper examines the effects of aperture jitter for a number of "typical" software radio GNSS receivers. A jitter specification is derived which restricts the noisy effects due to jitter to 10dB below thermal noise. It transpires that regardless of the new signals that are selected to accompany it, it is the L1 signal that drives this jitter specification.

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“…As optical digital networks have been shown to transmit an aggregate of 10 Tb/s of data [2], they require low phase noise clocks for multiplexing the data streams on the entire network. Other applications requiring low phase noise clocks include sampling for analog to digital converters [3,4], clock recovery [5], and pulse sources [6]. The Optoelectronic Oscillator, heretofore referred to as the OEO, is a photonic system that can provide very low phase noise clock signals.…”

Section: Introductionmentioning

confidence: 99%

A Review of Optoelectronic Oscillators for High Speed Signal Processing Applications

Devgan

2013

ISRN Electronics

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The Optoelectronic Oscillator (OEO) was first demonstrated in 1996 as a low phase noise RF source. Low phase noise RF sources have uses for multiple applications, ranging from analog to digital converters to radar to metrology. In the past sixteen years, the OEO has been shown to be useful for other signal processing applications. This paper will provide a background of the OEO's principles of operation, as well as multiple examples of signal processing applications where the OEO can be used. The OEO can be applied to both analog and digital problems, providing new techniques to solve these challenges.

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On the jitter requirements of the sampling clock for analog-to-digital converters

Cited by 101 publications

References 6 publications

Design and analysis of a CMOS passive Σ∆ ADC for low power RF transceivers

Design and analysis of a CMOS passive Σ∆ ADC for low power RF transceivers

Aperture Jitter Effects in Software Radio GNSS Receivers

A Review of Optoelectronic Oscillators for High Speed Signal Processing Applications

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