Heavily P doped Si:P epitaxial layers have gained interest in recent times as a promising source-drain stressor material for n type FinFETs (Fin Field Effect Transistors). They are touted to provide excellent conductivity as well as tensile strain. Although the as-grown layers do provide tensile strain, their conductivity exhibits an unfavorable behavior. It reduces with increasing P concentration (P > 1E21 at/cm 3 ), accompanied by a saturation in the active carrier concentration. Subjecting the layers to laser annealing increases the conductivity and activates a fraction of P atoms. However, there is also a concurrent reduction in tensile strain (<1%). Literature proposes the formation of local semiconducting Si 3 P 4 complexes to explain the observed behaviors in Si:P [Z. Ye et al., ECS Trans., 50(9) 2013, p. 1007-1011. The development of tensile strain and the saturation in active carrier is attributed to the presence of local complexes while their dispersal on annealing is attributed to strain reduction and increase in active carrier density. However, the existence of such local complexes is not proven and a fundamental void exists in understanding the structure-property correlation in Si:P films. In this respect, our work investigates the reason behind the evolution of strain and electrical properties in the as-grown and annealed Si:P epitaxial layers using ab-initio techniques and corroborate the results with physical characterization techniques. It will be shown that the strain developed in Si:P films is not due to any specific complexes while the formation of Phosphorus-vacancy complexes will be shown responsible for the carrier saturation and the increase in resistivity in the as-grown films. Interstitial/precipitate formation is suggested to be a reason for the strain loss in the annealed films. The microelectronics industry is currently in the 14 nm node where 3 dimensional(3D) Si FinFET devices are already in production. Although new technologies and materials (e.g. Tunnel FETs, III-V channels, Ge channels etc.) have been proposed for the future transistor nodes, several technological and reliability challenges need to be overcome before those devices can be realized.1,2 Hence, the next couple of nodes (possibly up to 5 nm) may continue to be dominated by the Si FinFET technology. The performance of the Si FinFETs can be further scaled by the re-introduction of the source-drain S/D stressors that were first introduced in the 65 nm node for planar transistors. Typically, SiGe(B) S/D stressors that provide compressive stress are used for p type FinFETs 3 while Si:C(P) ones that provide tensile stress are for n-FinFETs. 4 Out of the two, the Si:C(P) stressors suffer from the problem of increasing resistivity with increasing C contents. 5,6 Subjecting the as-grown Si:C(P) layers to laser or spike annealing does not result in any significant improvement in the conductivity or carrier concentration. 5,6 Hence, instead of Si:C(P), heavily P doped Si:P films have gained prominent interest in recent times. ...