On the performance of hafnium-oxide-based negative capacitance FinFETs, with and without a spacer

Abstract

This paper reports a thorough investigation of the impacts of a spacer dielectric on the performance of HfO2-feroelectric-based NC-FinFETs for 10nm technology (gate length 22nm) as per IRDS with in comparison with similarly-sized conventional FinFETs by means of an industry standard technology computer aided design (TCAD) tool. It is found that, although a high-k spacer results in improved SS and ION, it increases delay due to enhanced gate capacitance for both types of devices. In spite of having higher gate capacitance for a given spacer, the delay is lower for the NC devices than the conventional devices with identical IOFF, which is due to higher ION in such devices. Comparing with the Baseline FinFET; ION, SS, threshold voltage, delay and power dissipation of NC-FinFET have been found to improve by 69%, 7%, 5%, 14% and 9%, respectively, when Si3N4 spacer is used. Implications of spacer on VDD scalability, delay and power dissipation of NC-FinFETs have also been investigated in one-to-one comparison with similarly-sized conventional FinFETs. If identical delay is considered in both the devices, higher active power dissipation due to enhanced gate capacitance is a concern for HfO2-feroelectric-based NC-FinFETs.