On the pseudo-subthreshold characteristics of polycrystalline-silicon thin-film transistors with large grain size

Li, T.-S.; Lin, Pole-Shang

doi:10.1109/55.215180

Cited by 53 publications

(19 citation statements)

References 6 publications

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“…Conventionally, the concept of subthreshold swing or S-factor is usually used to describe the quality of the turn on characteristics where the device is controlled solely by modulation of carriers in the channel by a gate voltage. As discussed in [9], the TFT characteristics are not Fig. 3.…”

Section: A Subthreshold Characteristicsmentioning

confidence: 98%

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Improved Off-Current and Subthreshold Slope in Aggressively Scaled Poly-Si TFTs With a Single Grain Boundary in the Channel

Walker

Mizuta

Uno

et al. 2004

IEEE Trans. Electron Devices

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Abstract-A polycrystalline-silicon thin-film transistor (TFT), with a single grain boundary (GB) present in the channel, is simulated using two-dimensional numerical simulation, which includes a model of deep trap states at GBs. It is observed that the potential barrier resulting from a GB in the channel acts to suppress current flowing through the channel when the barrier height is greater than the thermal voltage. The conduction mechanism in the subthreshold regime is clarified. The turn-on characteristics of the device are controlled primarily by gate-induced grain barrier lowering as opposed to modulation of carriers in the channel by the gate voltage. In the negative bias region it is found that suppression of the off current is aided by the GB potential barrier. Scaling of the various geometrical parameters of the device are investigated. Improved subthreshold characteristics, compared to an equivalent silicon-on-insulator (SOI) structure, are found for aggressively scaled devices, due to the presence of a GB in the channel.

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Section: A Subthreshold Characteristicsmentioning

confidence: 98%

“…The effect on the depletion layer width is similar to that resulting from an increase in doping density. This reduces the height of the potential barrier and causes the so-called gate induced grain barrier lowering (GIGBL) effect [8], [9].…”

Section: Theorem 1 (Setos Depletion Approximation Model)mentioning

confidence: 99%

Improved Off-Current and Subthreshold Slope in Aggressively Scaled Poly-Si TFTs With a Single Grain Boundary in the Channel

Walker

Mizuta

Uno

et al. 2004

IEEE Trans. Electron Devices

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“…2 are the dependence of the drain current I d on the gate-to-source voltage V gs of the singly implanted Types A and B TFTs, showing, respectively, n-and p-channel characteristics at a drain-to-source bias of |V ds | = 0.1 V. This verifies earlier reports [6] that the field-effect polarity of a SAME poly-Si TFT, similar to that of a conventional poly-Si TFT, is also controlled by the implanted species. The linearly extrapolated turn-on voltage V on [9], the field-effect mobility μ FE extracted from the maximum transconductance, and the slope of the pseudo subthreshold region S p [10] are extracted and summarized in Table II. Considering the 900 • C hightemperature anneal after the MIC, it is not surprising that a higher μ FE and a smaller S p were measured on the p-channel Type B TFTs than on the n-channel Type A TFTs [11].…”

Section: Resultsmentioning

confidence: 99%

A Reduced Mask-Count Technology for Complementary Polycrystalline Silicon Thin-Film Transistors With Self-Aligned Metal Electrodes

Zhang

Kwok

Wong

2009

IEEE Electron Device Lett.

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The inexpensive glass substrate for building conventional low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) imposes a ceiling on the TFT processing temperature. This results in a reduced efficiency of dopant activation and a high source/drain series resistance. A technique based on aluminum-induced crystallization of amorphous silicon has been applied to fabricate TFTs with low-resistance self-aligned metal electrodes (SAMEs). While at least two masked implantation steps are typically used for constructing the doped source and drain regions of conventional n-and p-channel TFTs in a complementary metal-oxide-semiconductor circuit technology, it is currently demonstrated that complementary SAME poly-Si TFTs can be constructed using a combination of a masked and a blanket source and drain implantation steps. The decrease in mask count reduces process complexity and cost. Control of ion channeling is the enabling factor behind the successful demonstration of the technology.Index Terms-Aluminum, complementary, metal source and drain, polycrystalline silicon (poly-Si), self-aligned electrodes, thin-film transistors (TFTs).

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“…However, this approach can cause a significant error in evaluating derivatives such as transconductance [3]. In addition, important input parameters, such as the threshold voltage, V th , are especially difficult to be unambiguously determined for TFTs, due to the existence of the pseudosubthreshold region [4,5] as shown in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

A New Surface Potential Based Poly-Si TFT Model for Circuit Simulation

Tsuji

Kuzuoka

Kishida

et al. 2006

2006 International Electron Devices Meeting

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A new surface potential based poly-Si TFT model for circuit simulation was developed, accounting for the influence of both deep and tail states across the band gap. The model describes the drain current for all regions of operation using the unified equation. Calculations using the drain current model produce results that are in good agreement with the measured I-V characteristics of poly-Si TFTs.

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On the pseudo-subthreshold characteristics of polycrystalline-silicon thin-film transistors with large grain size

Cited by 53 publications

References 6 publications

Improved Off-Current and Subthreshold Slope in Aggressively Scaled Poly-Si TFTs With a Single Grain Boundary in the Channel

Improved Off-Current and Subthreshold Slope in Aggressively Scaled Poly-Si TFTs With a Single Grain Boundary in the Channel

A Reduced Mask-Count Technology for Complementary Polycrystalline Silicon Thin-Film Transistors With Self-Aligned Metal Electrodes

A New Surface Potential Based Poly-Si TFT Model for Circuit Simulation

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