Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.
DOI: 10.1109/essder.2005.1546645
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On the scalability of source/drain current enhancement in thin film sSOI

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Cited by 21 publications
(11 citation statements)
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“…For fabrication of the strained Si nMOSFETs either a global technique based on the sSDOI method (sSOI devices), a local technique where the stress is induced by a tensile-strained Si 3 N 4 contact etch stop layer (sCESL devices) or a combination of both (sSOI + sCESL devices) have been used. Technological details of the strain engineering have been published before [14]. The split batch contained four different types of devices: standard SOI (D05), sSOI (D09), sSOI + sCESL (D07) and SOI + sCESL (D03).…”
Section: Methodsmentioning
confidence: 99%
“…For fabrication of the strained Si nMOSFETs either a global technique based on the sSDOI method (sSOI devices), a local technique where the stress is induced by a tensile-strained Si 3 N 4 contact etch stop layer (sCESL devices) or a combination of both (sSOI + sCESL devices) have been used. Technological details of the strain engineering have been published before [14]. The split batch contained four different types of devices: standard SOI (D05), sSOI (D09), sSOI + sCESL (D07) and SOI + sCESL (D03).…”
Section: Methodsmentioning
confidence: 99%
“…3 that the use of strained material only results in better transconductance (and hence mobility) for devices longer than 0.20 lm. It is known from the literature that uniaxially strained planar devices with CESL have an improvement in carrier mobility when the channel length is reduced , whereas the opposite happens for biaxially strained transistors [19], i. e. the mobility gain thanks to strain diminishes as L reduces. Although the remaining biaxial strain component in 20 nm wide FinFETs is very small, its result in terms of mobility improvement agrees to those noticed for planar devices.…”
Section: Basic Device Characteristicsmentioning
confidence: 97%
“…According to the results presented in Ref. [13] there is no appreciable difference on the improvements provided by uniaxially, biaxially or combined uniaxially-biaxially strained substrates on the transconductance except for W smaller than 0.18 lm. Thus, for a reduction on W by a factor of 2 one would have similar I DS and hence distortion characteristics, but an appreciable reduction of the required area.…”
Section: Operation In Linear Regionmentioning
confidence: 73%
“…The studied nMOS devices are from a 65 nm planar single gate technology with mesa isolation [13]. The gate stack is composed of 1.5 nm thick thermally grown oxynitride and 100 nm polysilicon.…”
Section: Device Characteristicsmentioning
confidence: 99%