On the technology and ecosystem of 3D / TSV manufacturing

Abstract

Three-dimensional (3D) die stacking using through silicon viae (TSV) promises significant improvements in performance, power consumption and size over traditional edgeconnected die stacking (e.g. wire bonds) or package -on-package (PoP) based approaches. 3D integrat ed circuits (3D -IC) using TSV will enable new system in package (SiP) applications, especially where ultra -high memory bandwidth at moderate power consumption is needed. This paper describes the technology elements for a succ essful implementation of TSV in high volume manufacturing (HVM) with special focus on the socalled "TSV mid" integration flow being developed at SEMATECH. The maturity and readiness of each process module for HVM is assessed.In addition to technological feasibility and manufacturing readiness, 3D-IC adoption requires an environment of agreed upon specifications, standards, and tools (3D ecosystem). Progress toward a well defined 3D ecosystem by SEMATECH and many other organizations is described in part III of this paper.

Three-Dimensional Coaxial Through-Silicon-Via (TSV) Design

“…However, if properly designed, both inner hole and outer shell can be simultaneously etched using a Si etch process and filled using a Cu-TSV process. Moreover, the processes for cylindrical TSVs of 5 µm in diameter and 50 µm in height (similar to the inner conductor) and annular TSVs (similar to the outer shell) are demonstrated [5], [6]. Therefore, we believe that a fabrication process for coaxial TSVs can be developed.…”

Backside TSV protrusion induced by thermal shock and thermal cycling

“…A key component in 3D integration technology is the throughsilicon-via (TSV), which electrically connects multiple strata of ICs vertically, enabling high-performance, highfunctionality, compact heterogeneous systems with high data bandwidth and speed, and low power and cost. Substantial research is being conducted on other aspects of TSVs, such as design and processing development [1][2][3][4][5][6][7][8][9]. The objective of this paper is to investigate thermal-mechanical failure mechanisms of TSV-based 3D interconnect structures.…”

“…3D integration, which stacks and connects different materials, technologies, and functional components vertically, can overcome some limits encountered in planar ICs [1][2][3][4][5][6]. A key component in 3D integration technology is the throughsilicon-via (TSV), which electrically connects multiple strata of ICs vertically, enabling high-performance, highfunctionality, compact heterogeneous systems with high data bandwidth and speed, and low power and cost.…”

“…Such scaling will reach physical, technological or economic limits. Overcoming these limits requires alternative solutions, thus generating great interest in three-dimensional (3D) integration [1][2][3][4][5][6].…”

BMD impact on silicon fin defect at TSV bottom

“…Three‐dimensional (3D) integration, which stacks and connects different materials, technologies and functional components vertically, can overcome some limits encountered in planar integrated circuits (ICs) and traditional electronic packaging [1–3]. A key component in 3D integration technology is the through‐silicon via (TSV), which electrically connects multiple strata of ICs vertically, enabling high‐performance, high functionality, compact heterogeneous systems with high data bandwidth and speed, and low power and low cost.…”