Three-Dimensional Coaxial Through-Silicon-Via (TSV) Design

Xu, Zheng; Lü, Jian–Qiang

doi:10.1109/led.2012.2207703

Cited by 81 publications

(41 citation statements)

References 8 publications

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“…The integral in (2) becomes (9) Utilizing the same method above, we can acquire and as (10) and (11). When , (8), (10), and (11) coincide with the results proposed for cylindrical TSVs in [3] and [4] (10) (11) where , , , and .…”

Section: A Electrical Model Of Partial Inductance Of Tapered Tsvmentioning

confidence: 52%

“…Since is much larger than 1, can be approximated as . Using integral (6) and can finally be calculated as (5) and (7) Therefore, the self-partial inductance can be obtained by (8). As the current tends to move toward the surface of TSVs when frequency increases, the internal inductance goes to zero and is excluded in our calculations (8) Next, we determine the mutual partial inductance.…”

Section: A Electrical Model Of Partial Inductance Of Tapered Tsvmentioning

confidence: 99%

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Parasitic Inductance of Non-Uniform Through-Silicon Vias (TSVs) for Microwave Applications

Liu

Zhu

Yang

et al. 2015

IEEE Microw. Wireless Compon. Lett.

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In this letter, the parasitic inductance of tapered ground-signal-ground (GSG) type through-silicon via (TSV) pair used in high speed three-dimensional integrated circuits (3-D ICs) are proposed. Rigorous closed-form formulas of the inductance, exploiting loop and partial inductances, are derived based on the geometric information with frequency up to 20 GHz, which also cover the cylinder and GS-mode TSVs. The proposed models are in good agreement with the 3-D electromagnetic (EM) simulator and measurement results with maximum errors of 8%.Index Terms-Ground-signal-ground (GSG), high speed threedimensional (3D) integrated circuit (IC), inductance modeling, tapered through-silicon vias (TSVs).

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Section: A Electrical Model Of Partial Inductance Of Tapered Tsvmentioning

confidence: 52%

Section: A Electrical Model Of Partial Inductance Of Tapered Tsvmentioning

confidence: 99%

Parasitic Inductance of Non-Uniform Through-Silicon Vias (TSVs) for Microwave Applications

Liu

Zhu

Yang

et al. 2015

IEEE Microw. Wireless Compon. Lett.

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“…8 is 1.43%. In addition, the capacitances with a depletion layer are calculated using (9) and (10) and simulated with CST EMS. Due to less mobile charge carriers, the depletion region is modeled as a lossless silicon in our simulation [26], [27]. The maximum depletion radius r max is calculated using the method in [10].…”

Section: A Verification Of the Insulator Capacitance Expressionmentioning

confidence: 99%

Capacitance Expressions and Electrical Characterization of Tapered Through- Silicon Vias for 3-D ICs

Wang

Zhang

2015

IEEE Trans. Compon., Packag. Manufact. Technol.

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Closed-form expressions of the parasitic insulator capacitance and the substrate capacitance for tapered throughsilicon vias (T-TSVs) are proposed. The expressions are suitable for TSVs with high aspect ratio (thin and long). The maximum percentage errors between the calculated and simulated results for the insulator capacitance and the substrate capacitance are 1.86% and 3.75%, respectively. Then the equivalent circuit model of the T-TSV signal-ground pair is established and validated by comparison with the full-wave simulation results. Furthermore, the electrical characteristics of the T-TSV are evaluated with the proposed expressions. The results indicate that the T-TSV has longer latency and less crosstalk than the cylindrical TSVs. Index Terms-Insulator capacitance, metal-oxidesemiconductor (MOS) effect, substrate capacitance, tapered through-silicon vias (T-TSVs).2156-3950 . Her current research interests include microwave and millimeter-wave integrated circuits, electromagnetic compatibility, and microstrip antenna.

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“…1, where, M1, D, M2, and Si represent the cylindrical TSV metal (Cu), dielectric (SiO 2 ), tubular TSV metal, and silicon wafer, respectively. Table I lists the size parameters according to the current 3D TSV technology [4].…”

Section: Analytical Modelmentioning

confidence: 99%

Thermo-mechanical performance of Cu and SiO<sub>2</sub> filled coaxial through-silicon-via (TSV)

Wang

Zhu

Yang

et al. 2013

IEICE Electron. Express

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Analytical model for thermal stress in silicon induced by coaxial Through-silicon-via (TSV) is proposed. ANSYS is employed to verify the proposed model. It is shown that the average errors are ～2.5% for Cu and SiO 2 filled coaxial TSV. Based on the analytical model, thermo-mechanical performance of coaxial TSV is studied. Design guide lines for coaxial TSV are also given: 1) the smaller the sizes of metal parts, especially the outer metal shell, the better the thermo-mechanical performance; and 2) the dielectric size and the TSV height play unimportant roles on the thermal stress state.

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Three-Dimensional Coaxial Through-Silicon-Via (TSV) Design

Cited by 81 publications

References 8 publications

Parasitic Inductance of Non-Uniform Through-Silicon Vias (TSVs) for Microwave Applications

Parasitic Inductance of Non-Uniform Through-Silicon Vias (TSVs) for Microwave Applications

Capacitance Expressions and Electrical Characterization of Tapered Through- Silicon Vias for 3-D ICs

Thermo-mechanical performance of Cu and SiO<sub>2</sub> filled coaxial through-silicon-via (TSV)

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