Thermo-mechanical performance of Cu and SiO&lt;sub&gt;2&lt;/sub&gt; filled coaxial through-silicon-via (TSV)

Wang, Fengjuan; Zhu, Zhangming; Yang, Yintang; Liu, Xiaoxian; Ding, Ruixue

doi:10.1587/elex.10.20130894

Cited by 9 publications

(5 citation statements)

References 5 publications

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“…Compared with the reported work in ref. [32], it can be seen that the peak stress is about 562 MPa when the cylindrical metal diameter is 7 µm. However, the peak stress of the developed method is 85.28 MPa.…”

Section: Comparison and Discussionmentioning

confidence: 96%

Thermal-Stress Coupling Optimization for Coaxial through Silicon Via

et al. 2023

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In this paper, a thermal-stress coupling optimization strategy for coaxial through silicon via (TSV) is developed based on the finite element method (FEM), artificial neural network (ANN) model and particle swarm optimization (PSO) algorithm. In order to analyze the effect of design parameters on the thermal-stress distribution of coaxial TSV, the FEM simulations of coaxial TSV are conducted by COMSOL Multiphysics. The structure of coaxial TSV is symmetric. The mapping relationships between the design parameters and performance indexes are described by ANN models based on the simulation data of FEM. In addition, the multi-objective optimization function is formulated based on the desired performance indexes, and then the design parameters are optimized by the modified PSO algorithm. Based on the optimized design parameters, the effectiveness of the developed method is validated by FEM simulations. The simulated performance indexes agree well with the desired ones, which implies that the design parameters of coaxial TSV can be optimized to control the thermal-stress distribution. Therefore, the thermal-stress coupling optimization of coaxial TSV can achieve thermal-stress management to improve its reliability.

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Section: Comparison and Discussionmentioning

confidence: 96%

Thermal-Stress Coupling Optimization for Coaxial through Silicon Via

et al. 2023

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“…Qiu et al [ 23 ] performed electrical-thermal co-simulation with consideration of the temperature dependence of the metal-oxide-semiconductor effect for CTSV by using equivalent electrical and thermal circuit models. Wang et al [ 24 ] proposed an analytical model for the thermal stress caused by the CTSV and gave guidelines for the design of the CTSV. Dong et al [ 25 ] presented an accurate TSV thermal mechanical stress analytical model, which is verified by FEM.…”

Section: Introductionmentioning

confidence: 99%

Efficient Thermal-Stress Coupling Design of Chiplet-Based System with Coaxial TSV Array

Wang

Chen

et al. 2023

Micromachines

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In this research, an efficient thermal-stress coupling design method for a Chiplet-based system with a coaxial through silicon via (CTSV) array is developed by combining the support vector machine (SVM) model and particle swarm optimization algorithm with linear decreasing inertia weight (PSO-LDIW). The complex and irregular relationship between the structural parameters and critical indexes is analyzed by finite element simulation. According to the simulation data, the SVM model is adopted to characterize the relationship between structural parameters and critical indexes of the CTSV array. Based on the desired critical indexes of the CTSV array, the multi-objective evaluation function is established. Afterwards, the structural parameters of the CTSV array are optimized through the PSO-LDIW algorithm. Finally, the effectiveness of the developed method is verified by the finite element simulation. The simulated peak temperature, peak stress of the Chiplet-based system, and peak stress of the copper column (306.16 K, 28.48 MPa, and 25.76 MPa) well agree with the desired targets (310 K, 30 MPa, and 25 MPa). Therefore, the developed thermal-stress coupling design method can effectively design CTSV arrays for manufacturing high-performance interconnect structures applied in Chiplet-based systems.

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“…By now, the electrical and thermo-mechanical performances of C-TSV-based 3D IC have been studied sufficiently [5,6,7,8]. However, there is hardly research focusing on the temperature performance and thermal management.…”

Section: Introductionmentioning

confidence: 99%

Thermal management of coaxial through-silicon-via (C-TSV)-based three-dimensional integrated circuit (3D IC)

Wang

2016

IEICE Electron. Express

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Abstract:The analytical temperature model of coaxial through-silicon-via (C-TSV)-based three-dimensional integrated circuit (3D IC) is developed based on the Fourier' law of heat transfer and energy conservation, and is verified by employing ANSYS. Based on the theoretical model, several design guidelines are concluded. From the point of thermal management, 1) TSV should be inserted with high density; 2) Cu is a better material than Al and W; 3) the 3D IC layer should be as few as possible; 4) the silicon substrate thickness should be as thin as possible; 5) the temperature-sensitive modules should be placed near TSV and heat sink.

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Thermo-mechanical performance of Cu and SiO<sub>2</sub> filled coaxial through-silicon-via (TSV)

Cited by 9 publications

References 5 publications

Thermal-Stress Coupling Optimization for Coaxial through Silicon Via

Thermal-Stress Coupling Optimization for Coaxial through Silicon Via

Efficient Thermal-Stress Coupling Design of Chiplet-Based System with Coaxial TSV Array

Thermal management of coaxial through-silicon-via (C-TSV)-based three-dimensional integrated circuit (3D IC)

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