On the Use of a SiGe Spike in the Emitter to Improve the $f_{T}\hbox{xBV}_{\rm CEO}$ Product of High-Speed SiGe HBTs

Choi, L.J.; Huylenbroeck, Stefaan Van; Piontek, A.; Sibaja-Hernandez, A.; Kunnen, E.; Meunier-Beillard, P.; Noort, W.D. van; Hijzen, E.A.; Decoutere, Stefaan

doi:10.1109/led.2007.892366

Cited by 13 publications

(2 citation statements)

References 6 publications

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“…The f t BV CEO product can be improved by increasing the base current in SiGe HBTs with a SiGe spike inside the emitter [38]. This technique would provide low current gain value as discussed in the paper.…”

Section: Scaling Of Epi Layer Thickness Of Soi Hbtmentioning

confidence: 99%

Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOI CMOS Technology

Misra

Qureshi²

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved f t BV CEO product (397 GHzV). As the BV CEO value is higher for low value of epi layer doping, higher supply voltage can be used to increase the f t value of the HBT. At 1.8 V V CE , the f t BV CEO product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV f t BV CEO product at 1.2 V V CE ). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

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Section: Scaling Of Epi Layer Thickness Of Soi Hbtmentioning

confidence: 99%

Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOI CMOS Technology

Misra

Qureshi²

2014

JSTS:Journal of Semiconductor Technology and Science

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“…This can be achieved by reducing the minority carrier lifetime in the emitter [6]. By using SiGe in the emitter the BV CEO can be increased up to 30%, without reduction of the f T [7]. This is illustrated in Figure 4.…”

Section: Emitter Engineeringmentioning

confidence: 99%

The Versatile Use of SiGe for High-Performance Devices

Hijzen¹,

Donkers²,

Meunier-Beillard³

et al. 2008

ECS Trans.

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Apart from the widely used bandgap engineering in the base of Hetero-junction Bipolar Transistors (HBTs) and strain engineering in CMOS SiGe has many other possible application in Si technology. This paper will discuss several examples, both within and outside (Bi)CMOS technology. For instance, SiGe bandgap engineering can be used in power diodes. Other possibilities make use of the fact that SiGe can be etched selectively towards Si. This allows, for example, creation of cavities in the silicon substrate. These can be used for, e.g., reduction of parasitic capacitance, device isolation, or electric field shaping. IntroductionThe ever increasing speed requirements for, primarily, wireless applications has so-far been the main driver of the SiGe epitaxy research. This has resulted in processes with good manufacturability that are routinely used in high-performance BiCMOS processes. The development has always been driven by the need to create thin base layers with a different band-gap than the emitter (e.g. [1]). Over time also different applications of SiGe epitaxy have emerged. The one which is probably being explored most at the moment is the use for strain engineering for mobility enhancement in MOS transistors. The properties of SiGe are, however, also interesting for many more applications. The band-gap engineering aspect, for instance, can also be used to enhance switching diode performance, as will be shown below. Another interesting application makes use of the possibility to reduce carrier lifetime with SiGe, which can be used in emitters of HBTs to reduce the current gain, and hence increase breakdown voltage. Then there is the interesting property of SiGe that it can be used as a sacrificial material, because of the possibility to etch it selectively with respect to silicon. This allows micromachining in the front-end of an IC process. Some applications of this technology are also discussed in this paper.

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Dual-material dual-oxide double-gate TFET for improvement in DC characteristics, analog/RF and linearity performance

et al. 2019

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On the Use of a SiGe Spike in the Emitter to Improve the $f_{T}\hbox{xBV}_{\rm CEO}$ Product of High-Speed SiGe HBTs

Cited by 13 publications

References 6 publications

Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOI CMOS Technology

Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOI CMOS Technology

The Versatile Use of SiGe for High-Performance Devices

Dual-material dual-oxide double-gate TFET for improvement in DC characteristics, analog/RF and linearity performance

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