On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects

Accurate capture of timing parameters in inductively-coupled on-chip interconnects

“…This is in contrast to the short-range capacitive coupling in which only the mutual capacitances between adjacent lines are significant [9,14,8]. In Figure 2 one can also observe that the simple RLC model cannot accurately estimate the cross-talk.…”

“…Nevertheless, as seen in Figure 3 and in Table 1, the propagation delay may increase or decrease compared to the RC model prediction. Moreover, those delays are strongly correlated to the input data pattern [1,14,17]. Table 1 shows that for our simulation settings, the bestcase switching patterns for the RC model are worst-case ones for the RLMC model and vice-versa.…”

“…However, for several transition activity patterns, in the case of a toggle in the fourth-order neighbour, the voltage glitch predicted by inductive coupling may be even more than one order of magnitude larger than the one predicted by the RLC and RC models. More details about crosstalk noise for quiet and switching can be found in [2] and [14].…”

Impact of mutual inductance on timing in nano-scale SoC

“…Impacts of on-chip inductance on signal propagation delay have been discussed [1]- [4] for 1 GHz or higher clock frequencies. The articles [1][2] revealed effects of on-chip self-inductance and then proposed methods for screening interconnects which should be treated as RLC models [5] [6], rather than the conventional RC expressions [7].…”

“…As for the recent System-on-a-Chip (SoC) applications including 4K8K HDTV processing [8], processor cores need more speed to complete the required operations. Towards further high clock frequencies, the articles [3] [4] pointed out necessity of taking into consideration the inductive coupling effects in timing analysis. In order to reappear the inductive coupling effects, we have to extract the mutual-inductance (M ) in addition to the loop self-inductance (L) [9] [10].…”