Optical 4x4 hitless Silicon router for optical Networks-on-Chip (NoC): erratum

Sherwood-Droz, Nicolás; Wang, Howard; Chen, Long; Lee, Benjamin G.; Biberman, Aleksandr; Bergman, Keren; Lipson, Michal

doi:10.1364/oe.16.019395

Cited by 69 publications

(97 citation statements)

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“…Figure 1A illustrates the optical resonance of the microring and its shift with applied electrical bias [12]. In their most basic capacity they can serve as effective filters [13], switches [14,15], and modulators [16,17]. Additionally, microrings can be cascaded along the same waveguide bus, with each microring being offset to provide functionality for a specific wavelength.…”

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confidence: 99%

Resolving the thermal challenges for silicon microring resonator devices

2014

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Silicon microring resonators have been hailed for their potential use in next-generation optical interconnects. However, the functionality of silicon microring based devices suffer from susceptibility to thermal fluctuations that is often overlooked in their demonstrated results, but must be resolved for their future implementation in microelectronic applications. We survey the emerging efforts that have been put forth to resolve these thermal susceptibilities and provide a comprehensive discussion of their advantages and disadvantages.Keywords: integrated photonics; microring resonators; optical interconnects; silicon photonics. The growing bandwidth needs within data applications have motivated the replacement of traditionally electronic links with optical links for information networks as diverse as data centers, supercomputers, and fiber-optic access networks [1,2]. Applications such as these stress the traditional portfolio of optical components, rebalancing the emphasis from expensive high-performance components towards low-cost high-volume components that can be closely integrated with electronics. With these considerations in mind, the silicon photonics platform has received wide attention for its ability to deliver the necessary bandwidth required at an economy-of-scale that will be enabled by its compatibility with CMOS fabrication processes [3].Within the silicon photonic platform, traditional optical components such as low-loss waveguides [4], lowloss waveguide crossings [5], high-speed mach-zhender modulators (MZM) [6], arrayed waveguide-gratings [7], and efficient photodetectors [8,9] have been demonstrated. Leveraging the high index contrast between silicon and silicon-on-insulator, the aforementioned components have been shown with much smaller footprints than their counterparts in more conventional optical platforms. For active devices, these smaller footprints directly translate to higher energy-efficiencies.In addition to providing these improvements in footprint and energy-efficiency for traditional devices, the high-index contrast present in the silicon photonic platform enables the effective use of microring-based devices. A microring is a traveling wave resonator consisting of a ring structure side-coupled to a bus waveguide. While they have also been demonstrated in other material platforms, the high-index contrast of silicon and silicon-oninsulator has allowed them to be manifested as small as 1.5 µm in radius [10], and when used in conjunction with the free-carrier dispersion effect [11], well into Ghz-rate bandwidth. Figure 1A illustrates the optical resonance of the microring and its shift with applied electrical bias [12]. In their most basic capacity they can serve as effective filters [13], switches [14,15], and modulators [16,17]. Additionally, microrings can be cascaded along the same waveguide bus, with each microring being offset to provide functionality for a specific wavelength. In this manner, the microring lends itself naturally for wavelength-divisionmultiplexed ...

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confidence: 99%

Resolving the thermal challenges for silicon microring resonator devices

2014

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“…In 2008, Sherwood-Droz et al [63] demonstrated the spaceswitched 4×4 hitless optical routers by utilizing thermal tuning MRR switches. The dynamic TO tuning of MRRs needs power consumption and additional switching time (the TO tuning speed is very low, in the order of 10 kHz).…”

Section: Si Mrr-based Wavelength-selective Non-blocking Optical Routersmentioning

confidence: 99%

Silicon photonic network-on-chip and enabling components

Qiu

et al. 2013

Sci. China Technol. Sci.

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As the transistor's feature scales down and the integration density of the monolithic circuit increases continuously, the traditional metal interconnects face significant performance limitation to meet the stringent demands of high-speed, low-power and low-latency data transmission for on-and off-chip communications. Optical technology is poised to resolve these problems. Due to the complementary metal-oxide-semiconductor (CMOS) compatible process, silicon photonics is the leading candidate technology. Silicon photonic devices and networks have been improved dramatically in recent years, with a notable increase in bandwidth from the megahertz to the multi-gigahertz regime in just over half a decade. This paper reviews the recent developments in silicon photonics for optical interconnects and summarizes the work of our laboratory in this research field. interconnects, optical technology, complementary metal-oxide-semiconductor (CMOS), silicon photonics Citation:Hu T, Qiu C, Yu P, et al. Silicon photonic network-on-chip and enabling components.

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“…7(a) yields little benefit. Shacham et al proposed a fully optical 2-D torus with a combination of radix-4 blocking routers and specialized radix-2 injection and ejection routers [18], and others later explored radix-4 nonblocking routers [37]. Poon et al survey a variety of designs for optical routers that can be used in on-chip multistage nanophotonic networks [38].…”

Section: B Microarchitectural-level Designmentioning

confidence: 99%

Designing Chip-Level Nanophotonic Interconnection Networks

Batten

Joshi

Stojanović

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Abstract-Technology scaling will soon enable high-performance processors with hundreds of cores integrated onto a single die, but the success of such systems could be limited by the corresponding chip-level interconnection networks. There have been many recent proposals for nanophotonic interconnection networks that attempt to provide improved performance and energy-efficiency compared to electrical networks. This paper discusses the approach we have used when designing such networks, and provides a foundation for designing new networks. We begin by briefly reviewing the basic silicon-photonic device technology before outlining design issues and surveying previous nanophotonic network proposals at the architectural level, the microarchitectural level, and the physical level. In designing our own networks, we use an iterative process that moves between these three levels of design to meet application requirements given our technology constraints. We use our ongoing work on leveraging nanophotonics in an on-chip title-to-tile network, processor-to-main-memory network, and dynamic random-access memory (DRAM) channel to illustrate this design process.

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Optical 4x4 hitless Silicon router for optical Networks-on-Chip (NoC): erratum

Cited by 69 publications

References 1 publication

Resolving the thermal challenges for silicon microring resonator devices

Resolving the thermal challenges for silicon microring resonator devices

Silicon photonic network-on-chip and enabling components

Designing Chip-Level Nanophotonic Interconnection Networks

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