Optimal design of synchronous circuits using software pipelining techniques

Boyer, Francois-Raymond; Aboulhamid, E.M.; Savaria, Yvon; Bennour, Imed Eddine

doi:10.1109/iccd.1998.727024

Cited by 15 publications

(52 citation statements)

References 10 publications

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“…We represent the scheduling sequences relations among different transitions within the periodic clock framework and by a subtyping relation so that the throughput constraints can be inferred. We show that our method gives a result compatible to [10]; 2) Synthesis of the fractional synchronizer. We employ ideas from the periodic clock calculus to infer the number of fractional synchronizers used at each join transition (the transition with multiple inputs).…”

mentioning

confidence: 58%

“…(13) implies that the p th firing of S2 should be no earlier than the (p − 1) th firing of S0 plus one instant, which gives the same relation presented in [10]. Therefore, the schedule of this marked graph can also be obtained by BellmanFord's algorithm to find the longest paths to and from a chosen transition.…”

Section: (7)mentioning

confidence: 91%

“…Inequality (10) gives the upper bound of the throughput for T 0 → T 2 → T 0 and Inequality (11) gives the upper bound of the throughput for T 0 → T 1 → T 3 → T 0. Therefore our analysis is compatible with the problem of finding the minimum throughput of all elementary cycles [12].…”

Section: (7)mentioning

confidence: 99%

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Analysis of scheduled Latency insensitive systems with periodic clock calculus

Xue

Shukla

2009

2009 IEEE International High Level Design Validation and Test Workshop

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Originally the Latency insensitive protocols (LIP) were invented to make a system elastic to the interconnect latencies using handshaking signals such as 'valid' and 'stall'. These require extra signals leading to area overhead and may affect throughput of the system. To optimize away some of these overheads, scheduled LIPs were proposed which replaced the complex handshake control blocks by a central scheduling scheme. One can view a scheduled LIP based design as a system where within each strongly connected component of the system, the modules and the relay stations are scheduled by activation signals, which can be thought of as infinite sequence of '1's and '0's. If such sequences are periodic, one can view them as periodic clocks. Given the advances in periodic clock calculus in the synchronous programming context, in this paper, we analyze the LIP scheduling problem within the framework of periodic clock calculus. Such analysis provides straight forward algorithms to compute the throughput of scheduled LIP based systems . Within this framework, we also propose a method to synthesize fractional synchronizers. Fractional synchronizers are used to equalize cycles with different throughputs. Our method can determine the numbers and the scheduling sequences of such fractional synchronizers using the periodic clock calculus.

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confidence: 58%

Section: (7)mentioning

confidence: 91%

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Analysis of scheduled Latency insensitive systems with periodic clock calculus

Xue

Shukla

2009

2009 IEEE International High Level Design Validation and Test Workshop

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“…For example, retiming [4] can minimize the worst case clock period by moving in circuit registers. Also Software pipelining was a good approach to generate optimal clocking schemes [5], better that retiming when longest paths between registers cannot be equalized; registers are then activated at non uniform time intervals, like what we propose here. But these methods take in account static worst case delays only, not the delays variations according to dynamic conditions.…”

Section: Related Workmentioning

confidence: 97%

Implementation of a Cycle by Cycle Variable Speed Processor

Epassa

Boyer

Savaria

2005 IEEE International Symposium on Circuits and Systems

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This paper presents an automatic variable speed processor (VSP) with the ability to change its clock rate on a cycle by cycle basis, according to program instructions being in the pipeline. To demonstrate the concept, we are using an Altera Nios Processor coupled to a Variable Period Clock Synthesizer (VPCS) that is used as our variable speed clock generator. The clock period variations give a speedup, with little impact on energy consumption, and that speedup can be traded for energy reduction using voltage scaling. Our proposals are supported with a prototype implemented on the Altera Embedded System Development Board that embeds a Stratix FPGA.

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“…The technique is based on the software pipelining model of [19], which involves obtaining a schedule for each block. Similar to [16], the method handles increased cycle latencies by slowing down the circuit.…”

Section: B Frequency Constrained Wire-pipelined Circuitsmentioning

confidence: 99%

Designing optimized pipelined global interconnects: Algorithms and methodology impact

Nookala¹,

Sapatnekar²

2005 IEEE International Symposium on Circuits and Systems

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As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of latencies along paths in the circuit, and this can cause the implemented circuit to have a different functionality than was intended by the designer. Although it is possible to use design techniques that maintain the functionality of the circuit, an additional concern is a reduction in the throughput. This may be overcome by careful choices at various stages of design that impact the across-chip wire latencies. This paper surveys the published work on wire-pipelining, describes its impact on circuit as well as system level throughput, and outlines some of the problems to be resolved in formulating a wirepipelining centric strategy for physical design.

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Optimal design of synchronous circuits using software pipelining techniques

Cited by 15 publications

References 10 publications

Analysis of scheduled Latency insensitive systems with periodic clock calculus

Analysis of scheduled Latency insensitive systems with periodic clock calculus

Implementation of a Cycle by Cycle Variable Speed Processor

Designing optimized pipelined global interconnects: Algorithms and methodology impact

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