Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time

Abstract

In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-sizing problems have long been considered intractable. None of the existing approaches can guarantee optimality for general clock trees to the authors' best knowledge. In this paper, we present an -optimal zero-skew wire-sizing algorithm, ClockTune, which guarantees zero-skew with delay and area within distance to the optimal solutions in pseudo-polynomial time. Extensive experimental results show that our algorithm executes very efficiently in both runtime and memory usage. For example, ClockTune takes less than two minutes and 35MB memory to size an industrial clock tree with 3101 sink nodes within 2% to the optimal solution on a 533MHz Pentium III PC. Our algorithm can also be used to achieve useful clock skew to facilitate timing convergence and to incrementally adjust clock tree for design convergence and explore delay/power tradeoffs during design cycles. ClockTune is available on the web [13].

Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling

“…The power difference between minimum-delay and minimum-power solutions decreases with larger circuits and drops to 5% in r5. Compared with wiresizing along, which achieves an average of 3.3X delay reduction with 21.6% more power (with 1µm ≤ w ≤ 4µm) [5], simultaneous buffer-insertion/sizing and wire-sizing is not only much more efficient in reducing clock-delay but also more power efficient. Fig.…”

“…The details of transforming a subtree DC region to a branch DC region for wire-sizing is available in [5]. To capture the irregular shapes of the branch DC regions, sampling on wirewidth is applied and the intersection of the branch DC regions and a set of clock-delay scan-lines are obtained.…”

“…Recent work [5] uses a new approach to tackle wire-sizing problems for zero-skew clock-tree optimization. Since a zeroskew clock-tree can be characterized by its clock-delay and capacitance, the proposed algorithm captures the zero-skew design-space of each subtree with a two dimensional region, or a DC region, where the coordinates of the Y-axis and the Xaxis are the clock-delay and capacitance values.…”

“…In this paper, we extend the work of [5] and propose a zeroskew buffered clock-tree synthesis flow that generates processvariation robust and low-power clock-trees from a given set of clock sink nodes. First, we adopt the BB+DME [2] algorithm to generate the initial routings.…”

Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks

“…For example, changing buffer/wire size by one discrete step may result in a large change on skew and consequently a discrete optimization tends to have slow convergence. Unlike the cases using simple models, where many candidate solutions can be quickly evaluated and explored [10,12], using accurate model is too expensive for systematic solution search. Even worse, non-tree networks are more complicated to analyze than clock trees.…”