2014 IEEE 23rd Asian Test Symposium 2014
DOI: 10.1109/ats.2014.17
|View full text |Cite
|
Sign up to set email alerts
|

Optimal Redundancy Designs for CNFET-Based Circuits

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2015
2015
2023
2023

Publication Types

Select...
3
2

Relationship

0
5

Authors

Journals

citations
Cited by 5 publications
(1 citation statement)
references
References 27 publications
0
1
0
Order By: Relevance
“…It also suggests that a single-level optimization strategy is not enough to improve the overall yield of 2DM ICs. Instead, intrigued by the techniques from silicon industry, we can find adaptable circuit design solutions for 2DMs, such as fault-tolerant circuit design, layout optimization, [208] and machine learning-assisted methods. [209] Thus, a cross-level co-optimization strategy is indispensable, and has already been proposed for future advanced silicon CMOS nodes.…”
Section: Cross-level Co-optimizationmentioning
confidence: 99%
“…It also suggests that a single-level optimization strategy is not enough to improve the overall yield of 2DM ICs. Instead, intrigued by the techniques from silicon industry, we can find adaptable circuit design solutions for 2DMs, such as fault-tolerant circuit design, layout optimization, [208] and machine learning-assisted methods. [209] Thus, a cross-level co-optimization strategy is indispensable, and has already been proposed for future advanced silicon CMOS nodes.…”
Section: Cross-level Co-optimizationmentioning
confidence: 99%