Optimal subgraph covering for customisable VLIW processors

Lü, Yashuai; Shen, Li; Huang, Libo; Wang, Zhiying; Xiao, Nong

doi:10.1049/iet-cdt:20070104

Cited by 9 publications

(2 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These algorithms are generally time-consuming. To make them feasible, some pruning techniques, which depend on some parameters such as the extended ISA processor target and constraints, have been proposed (see, e.g., [25]). On the other hand, while the greedy approach is fast, the selected CI set is not necessarily the optimal set.…”

Section: B Selection Phasementioning

confidence: 99%

Considering the effect of process variations during the ISA extension design flow

Kamal

Afzali-Kusha

Safari

et al. 2013

Microprocessors and Microsystems

View full text Add to dashboard Cite

Abstract-In this paper, we present a technique for custom instruction (CI) extension considering process variations. Thetechnique bridges the gap between the high level custom instruction extension and chip fabrication in nanotechnologies. In particular, instead of using the conventional static timing analysis (STA), it utilizes statistical static timing analysis (SSTA). Therefore, the approach becomes probabilistic where the delay of each CI is modeled by a Probability Density Function (PDF).Using this probabilistic approach, different subsets of the CIs extension are identified to meet predefined constraints (identification phase) and eventually selected for realization to improve a given merit function (selection phase). In the identification phase, performance yield under both random and systematic variations is added as a constraint. Also, a pruning technique is proposed to decrease the runtime of the systematic variation modeling. The results show that the technique reduces the number of the CIs which need systematic variation modeling by about 24.6% for the cases studied in this work. In the selection phase, both greedy and branch-and-bound approaches are used. In the greedy approach, the conventional merit function based on the cycle saving and area is modified to include the performance yield. The results show the proposed merit function leads to about 3.2% increasing in the speedup. In the branch-and-bound method an effective pruning technique is described to reduce the runtime. The pruning technique is able to reduce the search space about 62%.

show abstract

Section: B Selection Phasementioning

confidence: 99%

Considering the effect of process variations during the ISA extension design flow

Kamal

Afzali-Kusha

Safari

et al. 2013

Microprocessors and Microsystems

View full text Add to dashboard Cite

show abstract

“…The very long instruction word (VLIW) architecture is widely adopted because it can explore the instruction level parallelism to achieve a high processing speed [10][11][12][13]. General VLIW architecture includes multiple special function units (FUs) that allow simultaneous execution for parallel operations [12,13].…”

Section: Introductionmentioning

confidence: 99%

Efficient matrix inversion based on VLIW architecture

Zhang

Shi

2014

J. of Syst. Eng. Electron.

View full text Add to dashboard Cite

Matrix inversion is a critical part in communication, signal processing and electromagnetic system. A flexible and scalable very long instruction word (VLIW) processor with clustered architecture is proposed for matrix inversion. A global register file (RF) is used to connect all the clusters. Two nearby clusters share a local register file. The instruction sets are also designed for the VLIW processor. Experimental results show that the proposed VLIW architecture takes only 45 latency to invert a 4 × 4 matrix when running at 150 MHz. The proposed design is roughly five times faster than the DSP solution in processing speed.

show abstract