Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems

Inagi, Masato; Takashima, Yoshinori; Nakamura, Yūichi; Takahashi, Atsushi

doi:10.1093/ietfec/e91-a.12.3539

Cited by 12 publications

(4 citation statements)

References 6 publications

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“…We performed experiments to evaluate our proposed method OTM-k compared to the ILP-based conventional method OTM-2 10) . ILP problem generation programs of both methods were implemented in C++, and the problems were solved by a well-known LP/ILP solver, GNU Linear Programming Kit (GLPK 7) ).…”

Section: Resultsmentioning

confidence: 99%

Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems

Inagi

Takashima

Nakamura

2010

IPSJ Transactions on System LSI Design Methodology

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Multi-FPGA prototyping systems are widely used to verify logic circuit designs. To implement a large circuit using such a system, the circuit is partitioned into multiple FPGAs. Subsequently, sub-circuits assigned to FPGAs are connected using interconnection resources among the FPGAs. Because of limited resources, time-multiplexed I/Os are used to accommodate all signals in exchange for system speed. In this study, we propose an optimization method of inter-FPGA connections for multi-FPGA systems with time-multiplexed I/Os to shorten the verification time by accelerating the systems. Our method decides whether each inter-FPGA signal is transferred by a normal I/O or a time-multiplexed I/O, which is slower than a normal I/O but can transfer multiple signals. Our method optimizes inter-FPGA connections not only between a single FPGA pair, but among all the FPGAs. Experiments showed that for four-way partitioned circuits, our method obtains an average system clock period 16.0% shorter than that of a conventional method.

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Section: Resultsmentioning

confidence: 99%

Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems

Inagi

Takashima

Nakamura

2010

IPSJ Transactions on System LSI Design Methodology

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“…The user applications call the function select() to monitor the active states of the serial ports corresponding to the device file descriptions in the table [9]. If all the monitored serial ports have no data to be transmitted, the thread enters into the waiting state.…”

Section: Receiving Process Of the Dual-mode Datamentioning

confidence: 99%

An Efficient Portable Navigation Device with GPS and BDS Positioning Capabilities

Lin¹,

Yao²,

An³

2015

IJMUE

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“…In [15,16], the authors proposed a new multiplexing approach based on the integer linear programming. The main objective of this study is to select which signals must be multiplexed and those which must not.…”

Section: Related Workmentioning

confidence: 99%

Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform

Turki

Marrakchi²,

Mehrez

et al. 2013

International Journal of Reconfigurable Computing

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Multi-FPGA hardware prototyping is becoming increasingly important in the system on chip design cycle. However, after partitioning the design on the multi-FPGA platform, the number of inter-FPGA signals is greater than the number of physical connections available on the prototyping board. Therefore, these signals should be time-multiplexed which lowers the system frequency. The way in which the design is partitioned affects the number of inter-FPGA signals. In this work, we propose a set of constraints to be taken into account during the partitioning task. Then, the resulting inter-FPGA signals are routed with an iterative routing algorithm in order to obtain the best multiplexing ratio. Indeed, signals are grouped and then routed using the intra-FPGA routing algorithm: Pathfinder. This algorithm is adapted to deal with the inter-FPGA routing problem. Many scenarios are proposed to obtain the most optimized results in terms of prototyping system frequency. Using this technique, the system frequency is improved by an average of 12.8% compared to constructive routing algorithm.

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Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems

Cited by 12 publications

References 6 publications

Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems

Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems

An Efficient Portable Navigation Device with GPS and BDS Positioning Capabilities

Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform

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