Optimization and analysis of high reliability 30–50V dual RESURF LDMOS

Kojima, Jun-ya; Matsuda, Jun‐ichi; Kamiyama, Masataka; Tsukiji, Nobukazu; Kobayashi, Haruo

doi:10.1109/icsict.2016.7998931

Cited by 8 publications

(4 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Specific on-resistance as a function of the breakdown voltage of the scaled down SJ-MGFET compare with the reported conventional LDMOSFETs and SJ-LDMOSFETs[33,34,35,36] devices.…”

mentioning

confidence: 80%

“…The simulations show that the SJ-MGFET with 0.25 µm gate length achieves a low R on,sp (V GS = 10 V ) of 2.24 mΩ.mm 2 and BV = 26 V with L drift = 0.875 µm and the SJ-MGFET with 0.5 µm gate length offers a R on,sp (V GS = 10 V ) of 7.68 mΩ.mm 2 and BV = 48 V with L drift = 1.75 µm, respectively. The SJ-MGFET scaled to the 0.5 µm gate length leads to 16% reduction in R on,sp compared to superjunction UMOSFET (SJ-UMOSFET) at the same BV rating [33], 73% reduction compared to Floating RESURF (FRESURF) at the same BV rating [34], 78% reduction compared to dual RESURF LDMOS at the same BV rating [35], and 85% reduction compared to isolated low NLD-MOS at the same BV rating [36]. The SJ-MGFET scaled to the 0.25 µm gate length has R on,sp lower by 90% compared to isolated low NLDMOS [36] at the same breakdown voltage rating.…”

Section: Scaling Approach and Structure Optimisation Of The Scaled Domentioning

confidence: 99%

See 1 more Smart Citation

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Adenekan

Holland

Kálna

2019

Microelectronics Reliability

View full text Add to dashboard Cite

The scaling of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 50 V) requires a subsequent optimisation of SJ unit. The scaling and the SJ optimisation are carried out with physically based commercial TCAD device simulations by Silvaco. The study is based on a meticulous calibration of drift-diffusion simulations against experimental characteristics of a 1 µm gate length SJ multigate MOSFET (SJ-MGFET) aiming at improving density, switching speed, drive current, breakdown voltage (BV), and specific on-resistance (R on,sp). We investigate scaling of the device architecture to improve the device performance by optimizing doping profile to achieve an avalanche-enabled device under a charge balanced condition. The optimised SJ-MGFETs scaled by a factor of 0.5 and 0.25, with a folded alternating U-shaped n/p-SJ drift region pillar of a width of 0.3 µm and a trench depth of 2.7 µm, achieve a low specific on-resistance (R on,sp) of 7.68 mΩ.mm 2 and 2.24 mΩ. mm 2 (V GS = 10 V) and BV of 48 V and 26 V , respectively. The scaled 0.5 µm and 0.25 µm gate length SJ-MGFETs offer a transconductance (g m) of 20 mS/mm and 56 mS/mm at a drain voltage of 0.1 V , respectively, greatly improving the levels of integration in a CMOS architecture.

show abstract

“…Specific on-resistance as a function of the breakdown voltage of the scaled down SJ-MGFET compare with the reported conventional LDMOSFETs and SJ-LDMOSFETs[33,34,35,36] devices.…”

mentioning

confidence: 80%

Section: Scaling Approach and Structure Optimisation Of The Scaled Domentioning

confidence: 99%

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Adenekan

Holland

Kálna

2019

Microelectronics Reliability

View full text Add to dashboard Cite

show abstract

“…Lateral diffused metal-oxide-semiconductor field-effect transistor (LDMOS) devices have been efficiently applied to ICs for power electronics, power managements and display driver, given their advantages of low ON-resistance and ability to withstand high operating voltages [10][11][12][13][14][15][16]. Therefore, design methods for each operating voltage devices to develop various HV and low-voltage devices by using single-process chips are crucial for many applications.…”

Section: Introductionmentioning

confidence: 99%

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

et al. 2020

View full text Add to dashboard Cite

An electrostatic discharge (ESD) event can negatively affect the reliability of integrated circuits. Therefore, improving on ESD immunity in high-voltage (HV) n-channel (n) lateral diffused metal–oxide–semiconductor field-effect transistor (HV nLDMOS) components through drain-side layout engineering was studied. This involved adjusting the operating voltage, improving the non-uniform turned-on phenomenon, and examining the effects of embedded-device structures on ESD. All proposed architectures for improving ESD immunity in this work were measured and evaluated using a transmission-line pulse system. The corresponding trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2) results of the tested devices were obtained. This paper first addresses the drift-region length modulation to design different operating voltages, which decreased as the drift region length and shallow trench isolation (STI) length shrunk. When an HV nLDMOS device decreased to the shortest drift region length, the Vt1 and Vh values were closest to 21.85, and 9.27 V, respectively. The It2 value of a low-voltage operated device could be increased to a maximum value of 3.25 A. For the channel width modulation, increasing the layout finger number of an HV LDMOS device did not really help the ESD immunity that because it may suffer the problem of non-uniform turned-on phenomenon. Therefore, adjusting the optimized channel width was the best one method of improvement. Furthermore, to improve the low ESD reliability problem of nLDMOS devices, two structures were used to improve the ESD capability. The first was a drain side—embedded silicon-controlled rectifier (SCR). Here, the SCR PNP-arranged type in the drain side had the best ESD capability because the SCR path was short and had been prior to triggering; however, it also has a latch-up risk and low Vh characteristic. By removing the entire heavily doped drain-side N+ region, the equivalent series resistance in the drain region was increased, so that the It2 performance could be increased from 2.29 A to 3.98 A in the structure of a fully embedded drain-side Schottky diode. This component still has sufficiently high Vh behaviour. Therefore, embedding a full Schottky-diode into an HV nLDMOS in the drain side was the best method and was efficient for improving the ESD/Latch-up abilities of the device. The figure of merit (FOM) of ESD, Latch-up, and cell area considerations improved to approximately 80.86%.

show abstract

“…Consequently, smaller transistors are more vulnerable to the electrostatic-discharge (ESD) transient, and have a considerably higher failure rate [ 1 , 2 , 3 , 4 , 5 , 6 ]. The laterally-diffused metal-oxide-semiconductor field-effect transistor (LDMOSs) are often used in many integrated circuits of automotive electronics, power management circuits, power electronics, and communication modules [ 7 , 8 , 9 , 10 , 11 , 12 ] under high-voltage operation situations, owing to their distinguished characteristics, including being able to operate at a high blocking voltage and high conduction current. Because the device structure of a high-voltage (HV) LDMOS is complicated, designing an ESD protection unit into HV circuits is challenging [ 13 , 14 , 15 , 16 , 17 , 18 , 19 ].…”

Section: Introductionmentioning

confidence: 99%

Sensing and Reliability Improvement of Electrostatic-Discharge Transient by Discrete Engineering for High-Voltage 60-V n-Channel Lateral-Diffused MOSFETs with Embedded Silicon-Controlled Rectifiers

Chen

2018

Sensors

View full text Add to dashboard Cite

High-voltage n-channel lateral-diffused metal-oxide-semiconductor field-effect transistor (nLDMOS) components, fabricated by a TSMC 0.25-μm 60-V bipolar-CMOS-DMOS (BCD) process with drain-side embedded silicon-controlled rectifier (SCR) of the n-p-n-arranged and p-n-p-arranged types, were investigated, in order to determine the devices’ electrostatic discharge (ESD)-sensing behavior and capability by discrete anode engineering. As for the drain-side n-p-n-arranged type with discrete-anode manners, transmission–line–pulse (TLP) testing results showed that the ESD ability (It2 value) was slightly upgraded. When the discrete physical parameter was 91 rows, the optimal It2 reached 2.157 A (increasing 17.7% compared with the reference sample). On the other hand, the drain-side SCR p-n-p-arranged type with discrete-anode manner had excellent SCR behavior, and its It2 values could be increased to >7 A (increasing >281.9% compared with the reference DUT). Moreover, under discrete anode engineering, the drain-side SCR n-p-n-arranged and p-n-p-arranged types had clearly higher ESD ability, except for the few discrete physical parameters. Therefore, using the anode discrete engineering, the ESD dissipation ability of a high-voltage (HV) nLDMOS with drain-side SCRs will have greater effectiveness.

show abstract

Optimization and analysis of high reliability 30–50V dual RESURF LDMOS

Cited by 8 publications

References 2 publications

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

Sensing and Reliability Improvement of Electrostatic-Discharge Transient by Discrete Engineering for High-Voltage 60-V n-Channel Lateral-Diffused MOSFETs with Embedded Silicon-Controlled Rectifiers

Contact Info

Product

Resources

About

Optimization and analysis of high reliability 30–50V dual RESURF LDMOS

Cited by 8 publications

References 2 publications

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

Sensing and Reliability Improvement of Electrostatic-Discharge Transient by Discrete Engineering for High-Voltage 60-V n-Channel Lateral-Diffused MOSFETs with Embedded Silicon-Controlled Rectifiers

Contact Info

Product

Resources

About

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications