Optimization of doping profile and isolation oxide thickness in bulk FinFETs using TCAD simulations

Scarlet, S. Priscilla; Nagarajan, Karthikeyan; Srinivasan, R.

doi:10.1109/iccpct.2013.6528897

2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT) 2013

DOI: 10.1109/iccpct.2013.6528897

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Optimization of doping profile and isolation oxide thickness in bulk FinFETs using TCAD simulations

S. Priscilla Scarlet¹,

Karthikeyan Nagarajan²,

R. Srinivasan³

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Cited by 3 publications

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“…This requires a careful design of punch-through stopper (PTS) doping to suppress the sub-channel leakage current at the bottom of the fin. 3,4 The PTS doping also causes carrier mobility degradations and serious threshold voltage (V TH ) variability in transistors. 5 Different from the bulk-Si FinFET, a FinFET fabricated on the SOI substrate (SOI FinFET) has an isolated fin channel naturally formed by the buried oxide.…”

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confidence: 99%

Self-Aligned Fin-On-Oxide (FOO) FinFETs for Improved SCE Immunity and Multi-VTH Operation on Si Substrate

Hong

2015

ECS Solid State Letters

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The paper proposed a simple and novel approach to fabricate Fin-On-Oxide (FOO) FinFETs on silicon (Si) substrates for improved electrical characteristics in scaled devices. Based on conventional bulk-Si FinFET integration flow, a special step of a fin notch etching is performed, followed by a process of liner oxidation and isolation-oxide filling and recess. The fin above the notch is physically isolated from the substrate and turns into a self-aligned FOO structure. The fabricated p-type FOO FinFETs have demonstrated excellent short-channel effect (SCE) characteristics with subthreshold slope (SS) of 69 mV/dec and drain-induced barrier lowering (DIBL) of 22 mV/V for a physical gate length (L G ) of 27 nm. For 14 nm devices, SS of 86 mV/dec and DIBL of 106 mV/V have been achieved, which are much better than those of the bulk-silicon FinFET counterpart with similar process. Meanwhile, the steady threshold voltage (V TH ) shifting by the substrate biasing is realized in the FOO FinFET without performance degradations. The linearity of the V TH on the bias voltage is −6 mV/V. The self-aligned FOO-FinFET with a simple process provides a promising method to improve the SCE immunity as well as provides the multi-V TH operation for the scaled FinFET on Si substrates for future ultra-low power circuit applications. With more than 10 years of continuous research and development, bulk-silicon (Si) FinFET has been commonly recognized as one of the most promising device architectures for the mass production of the most advanced CMOS integration circuits.1,2 Due to the multi-gates, such as the double or the triple gates on a narrow fin channel, FinFET has a well-controlled electrostatic integrity in the short channel even with the physical gate length (L G ) below 30 nm. However, the actual fin channel in the normal bulk-Si FinFET is within the fin body tied to the Si substrate. This requires a careful design of punch-through stopper (PTS) doping to suppress the sub-channel leakage current at the bottom of the fin.3,4 The PTS doping also causes carrier mobility degradations and serious threshold voltage (V TH ) variability in transistors.5 Different from the bulk-Si FinFET, a FinFET fabricated on the SOI substrate (SOI FinFET) has an isolated fin channel naturally formed by the buried oxide. SOI FinFET has the advantages of simplified integration process, reduced leakage and improved device variability. However, it suffers from a high-cost starting wafer and a series of process issues for integrating the high-voltage or the passive components on SOI substrates. As L G continuously scaling down, the short channel effect (SCE) and the channel substrate leakage in the transistor become more serious. The FinFETs with the physical isolation fin channels on conventional Si substrates become one of the most interesting research topics for scaling FinFETs technology in the future.Some papers reported the fabrication process of the advanced isolated structure on Si substrates with a complicated process. 6 For the first time, this let...

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confidence: 99%

Self-Aligned Fin-On-Oxide (FOO) FinFETs for Improved SCE Immunity and Multi-VTH Operation on Si Substrate

Hong

2015

ECS Solid State Letters

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Performance enhancement of junctionless silicon nanotube FETs using gate and dielectric engineering

Scarlet

Vinodhkumar

Srinivasan³

2020

J Comput Electron

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Optimization of nanometer bulk junctionless Trigate FET using gate and isolation dielectric engineering

Scarlet¹,

Srinivasan²

2018

Materials Science in Semiconductor Processing

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Optimization of doping profile and isolation oxide thickness in bulk FinFETs using TCAD simulations

Cited by 3 publications

References 9 publications

Self-Aligned Fin-On-Oxide (FOO) FinFETs for Improved SCE Immunity and Multi-VTH Operation on Si Substrate

Self-Aligned Fin-On-Oxide (FOO) FinFETs for Improved SCE Immunity and Multi-VTH Operation on Si Substrate

Performance enhancement of junctionless silicon nanotube FETs using gate and dielectric engineering

Optimization of nanometer bulk junctionless Trigate FET using gate and isolation dielectric engineering

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