Self-Aligned Fin-On-Oxide (FOO) FinFETs for Improved SCE Immunity and Multi-VTH Operation on Si Substrate

Abstract

The paper proposed a simple and novel approach to fabricate Fin-On-Oxide (FOO) FinFETs on silicon (Si) substrates for improved electrical characteristics in scaled devices. Based on conventional bulk-Si FinFET integration flow, a special step of a fin notch etching is performed, followed by a process of liner oxidation and isolation-oxide filling and recess. The fin above the notch is physically isolated from the substrate and turns into a self-aligned FOO structure. The fabricated p-type FOO FinFETs have demonstrated excellent short-channel effect (SCE) characteristics with subthreshold slope (SS) of 69 mV/dec and drain-induced barrier lowering (DIBL) of 22 mV/V for a physical gate length (L G ) of 27 nm. For 14 nm devices, SS of 86 mV/dec and DIBL of 106 mV/V have been achieved, which are much better than those of the bulk-silicon FinFET counterpart with similar process. Meanwhile, the steady threshold voltage (V TH ) shifting by the substrate biasing is realized in the FOO FinFET without performance degradations. The linearity of the V TH on the bias voltage is −6 mV/V. The self-aligned FOO-FinFET with a simple process provides a promising method to improve the SCE immunity as well as provides the multi-V TH operation for the scaled FinFET on Si substrates for future ultra-low power circuit applications. With more than 10 years of continuous research and development, bulk-silicon (Si) FinFET has been commonly recognized as one of the most promising device architectures for the mass production of the most advanced CMOS integration circuits.1,2 Due to the multi-gates, such as the double or the triple gates on a narrow fin channel, FinFET has a well-controlled electrostatic integrity in the short channel even with the physical gate length (L G ) below 30 nm. However, the actual fin channel in the normal bulk-Si FinFET is within the fin body tied to the Si substrate. This requires a careful design of punch-through stopper (PTS) doping to suppress the sub-channel leakage current at the bottom of the fin.3,4 The PTS doping also causes carrier mobility degradations and serious threshold voltage (V TH ) variability in transistors.5 Different from the bulk-Si FinFET, a FinFET fabricated on the SOI substrate (SOI FinFET) has an isolated fin channel naturally formed by the buried oxide. SOI FinFET has the advantages of simplified integration process, reduced leakage and improved device variability. However, it suffers from a high-cost starting wafer and a series of process issues for integrating the high-voltage or the passive components on SOI substrates. As L G continuously scaling down, the short channel effect (SCE) and the channel substrate leakage in the transistor become more serious. The FinFETs with the physical isolation fin channels on conventional Si substrates become one of the most interesting research topics for scaling FinFETs technology in the future.Some papers reported the fabrication process of the advanced isolated structure on Si substrates with a complicated process. 6 For the first time, this let...

State of the Art and Future Perspectives in Advanced CMOS Technology

“…The devices with different thickness of ALD TiN show the similar electrical parameters, while the reliability issues of devices are obviously different. Usually, the devices with thin ALD TiN layer show worse hot carrier injection (HCI) and better bias temperature instability (BTI) than that with thick ALD TiN due to the chlorine diffusion [ 10 , 296 ] and nitrogen diffusion [ 297 , 298 ], respectively. Therefore, it is key to restrain reliability degradation of advanced CMOS technology by controlling the process.…”

“…As a result, the most promising transistor architectures may be fin-on-insulator (FOI) Fin Field-Effect Transistor (FinFET) [ 8 , 9 , 10 , 11 ], scalloped fin FinFET [ 12 ], and NW field effect transistors (FETs) [ 13 , 14 , 15 ]. These new transistor designs have shown better control of short channel effects (SCEs), low leakage junctions, and high carrier mobility.…”

Miniaturization of CMOS

“…Thus, new device structures, new materials, and new integration approaches have to provide new solutions. Therefore, novel promising device architectures like fin-on-insulator (FOI) FinFET [8,9,10,11], scalloped fin FinFET [12], nanowire (NW) FETs, and the stacked NW device [13,14,15] have demonstrated great improvement for short channel effects (SCEs), leakage control, and higher electron and whole mobility. The fin-on-insulator (FOI) FinFET, fabricated on the bulk Si substrate with a special process takes both advantages of bulk FinFET and SOI technologies.…”

Special Issue: Silicon Nanodevices

“…As a result of CMOS evolution, a lot of integration difficulties have been overcome, enabling the architecture of CMOS technology to change from planar or 2D to 3D. During this technology development, many issues, e.g., contact resistance, defects and reliability, have arisen and have been solved, which could affect device performance [2,3]. As an approach at the end of the technology roadmap (3 nm node), Si channel material is being changed to SiGe or Ge material, and even III-V materials could be integrated in the future.…”