Optimization of process conditions of selective epitaxial growth for elevated source/drain CMOS transistor

Nakahata, Takumi; Sugihara, Kohei; Maruno, Shigemitsu; Abe, Yuji; Ozeki, Tatsuo

doi:10.1016/s0022-0248(02)01481-1

Cited by 11 publications

(8 citation statements)

References 8 publications

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“…As far as MOSFETs are concerned, the fact that they are aggressively scaled down following the International Technology Roadmap for Semiconductors [2] puts stringent requirements on the source/drain junctions in terms of doping, shallowness and abruptness. One rather elegant method of meeting these prerequisites is to use Si or SiGe raised sources and drains (RSD) selectively grown in the active regions on each side of the gate stack [3][4][5][6][7][8][9][10][11]. This way, very shallow, quite heavily doped junctions can be formed, more material can be used up for silicidation (with, e.g.…”

Section: Introductionmentioning

confidence: 99%

Selective epitaxial growth of boron- and phosphorus-doped Si and SiGe for raised sources and drains

Hartmann

Clavelier

Jahan

et al. 2004

Journal of Crystal Growth

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Section: Introductionmentioning

confidence: 99%

Selective epitaxial growth of boron- and phosphorus-doped Si and SiGe for raised sources and drains

Hartmann

Clavelier

Jahan

et al. 2004

Journal of Crystal Growth

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“…The growth temperature was set at under 700 C. Si 2 H 6 and Cl 2 gases were used as the gas source [8]. The pressure of the growth chamber during growth was less than 2 Â 10 À2 Pa. After the sidewalls were formed by etching with (a) CHF 3 /Ar plasma or (b) Cl 2 plasma using a 10% overetching step, the wafers were loaded into the UHV-CVD apparatus to grow the SEG-Si at 650 C for 20 min without preheating, during which the Si 2 H 6 and the Cl 2 flow rates were 1.5 and 0.05 sccm, respectively.…”

Section: Methodsmentioning

confidence: 99%

“…Therefore, we tried to flatten the SEG-Si surface and increase the growth rate of SEG-Si by optimizing the growth conditions at temperatures below 700 C. In our previous reports [8], it was revealed that the use of Cl 2 plasma also results in the very thin amorphous layer on the substrate surface, and that the amorphous layer could not be removed by the 850 C-preheating. The thickness of the amorphous layer was estimated at the less than one monolayer, which was difficult to detect by the XPS measurement [8]. It was also thought that the very thin amorphous layer caused the unevenness on the SEG-Si surface.…”

Section: Optimization Of the Process Conditions Of Segsi Growthmentioning

confidence: 99%

“…The amorphous layer is vaporized by the Si 2 H 6 dissociation in accordance with the deoxidation reaction of Si+SiO 2 -SiOm. When the deoxidation occurs more rapidly than SEG-Si growth, the SEG-Si surface is flattened [8]. Thus, it is necessary to achieve both the flatter surface of the SEG-Si layer and the greater productiveness that the amorphous layer is removed from the substrate surface in the initial stage of the SEG-Si growth.…”

Section: Optimization Of the Process Conditions Of Segsi Growthmentioning

confidence: 99%

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Low thermal budget selective epitaxial growth for formation of elevated source/drain MOS transistors

Nakahata

Sugihara

Abe

et al. 2004

Journal of Crystal Growth

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“…Selective epitaxial growth ͑SEG͒ by chemical vapor deposition ͑CVD͒ is commonly being used in ESD formation. [2][3][4][5] However, the thickness of silicon layers formed by SEG is limited by the onset of polysilicon nucleation on insulating layers. Variation of SEG-Si thickness over the surface has also been reported.…”

mentioning

confidence: 99%

Technique for Large Elevation of Source/Drain Using Implantation Mediated Selective Etching

Huda¹,

Sakamoto²,

Tanoue³

2003

Electrochem. Solid-State Lett.

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A process involving implantation mediated selective etching has been developed for source/drain elevation of metal-oxidesemiconductor devices. A 100 nm thick epitaxial silicon/polysilicon layer was formed on a patterned Si/SiO 2 structure by chemical vapor deposition ͑CVD͒ at 700°C. Samples were then implanted with 2 ϫ 10 14 /cm 2 argon at 140 keV in the ͗100͘ channeling direction, followed by 1 min annealing at 420°C. The polysilicon layer was then removed by wet etching with more than an order of magnitude selectivity over epitaxial silicon. The resulting structure of elevated silicon is free from faceting effects. The process is independent of sidewall/isolation materials, and not bound by thickness limits.Selective elevation of silicon on patterned structures has been studied for a long time. 1 The prospective application is on elevated source/drain ͑ESD͒ structures in ultralarge scale integration ͑ULSI͒ technology. 2 ESD regions in complementary metal-oxidesemiconductor ͑CMOS͒ devices provide the extra silicon thickness that allows the formation of silicide contacts for very shallow junctions. Selective epitaxial growth ͑SEG͒ by chemical vapor deposition ͑CVD͒ is commonly being used in ESD formation. 2-5 However, the thickness of silicon layers formed by SEG is limited by the onset of polysilicon nucleation on insulating layers. Variation of SEG-Si thickness over the surface has also been reported. 3,4 But, most important, there is a natural tendency of forming ͑111͒ and ͑311͒ facets along pattern edges during the SEG growth. 5 These facets result in thin or almost negligible elevation of source/drain region near the gate sidewall. This seems to be a bottleneck in the SEG technique as the source/drain metallization, and also the junction tends to be deeper along the gate sidewall, causing additional leakage and short channel effects, respectively. 6 Careful processing of the material and optimization of growth conditions have been used for facet-free epitaxy, but only up to a thickness of 80 nm. 7 In this paper, we report on an approach for elevation of source/drain without thickness limits or faceting problems. 100 nm thick selective elevation of silicon has been achieved on a Si/SiO 2 patterned structure. The process involves conventional nonselective CVD growth, followed by an implantation mediated selective etching. ExperimentalA 220 nm thick oxide was formed on silicon ͑001͒ by dry oxidation at 1100°C. Samples were then patterned along the ͗100͘ direction using standard lithography and reactive ion etching ͑RIE͒. Low pressure chemical vapor deposition ͑LPCVD͒ was done on the patterned samples at 700°C using a SiH 4 /H 2 gas flow. The CVD grown samples were implanted with argon at 140 or 200 keV with doses of 2 ϫ 10 14 or 4 ϫ 10 14 /cm 2 . The implantation was oriented along the ͗100͘ channeling direction. Implanted samples were annealed for 1 min at 420 or 500°C. A solution of HF:HNO 3 :CH 3 COOH ͑1:80:120͒ was used for wet etching. Etching depths were measured in a Sloan Dektak 3030 surface profile mea...

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Optimization of process conditions of selective epitaxial growth for elevated source/drain CMOS transistor

Cited by 11 publications

References 8 publications

Selective epitaxial growth of boron- and phosphorus-doped Si and SiGe for raised sources and drains

Selective epitaxial growth of boron- and phosphorus-doped Si and SiGe for raised sources and drains

Low thermal budget selective epitaxial growth for formation of elevated source/drain MOS transistors

Technique for Large Elevation of Source/Drain Using Implantation Mediated Selective Etching

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