Optimization of select gate transistor in advanced 3D NAND memory cell

Cho, Jin; Kimpton, Derek; Guichard, E.

doi:10.1109/sispad.2019.8870415

Cited by 3 publications

(1 citation statement)

References 4 publications

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“…In particular, since the number of slits for block-to-block separations is reduced to increase the chip density [11], the number of strings is expected to increase continuously; thereby, Y-mode program stress will be the main cause further diminishing the memory window. Second, since 3D NAND uses poly-silicon as channel material, the on/off characteristic of the select transistor is much worse than that of 2D NAND, and the off-state leakage current flows through the select gate in boosting mode, which weaken the program disturbance [13]. Third, since it is difficult to remove electrons in the polysilicon channel during the pre-charge operation due to the grain boundary trap [14,15], achieving high channel potential in boosting mode is very challenging.…”

Section: Improvement Of the Program Disturbmentioning

confidence: 99%

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

Park

Kim

2022

Applied Sciences

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The size of the memory market is expected to continue to expand due to the digital transformation triggered by the fourth industrial revolution. Among various types of memory, NAND flash memory has established itself as a major data storage medium based on excellent cell characteristics and manufacturability; as such, the demand for increasing the bit density and the performance has been rapidly increasing. In this paper, we will review the device operation algorithm and techniques to improve the cell characteristics and reliability in terms of optimization of individual program, read and erase operation, and system level performance.

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