Optimization of V/sub th/ roll-off in MOSFET's with advanced channel architecture-retrograde doping and pockets

Gwoziecki, R.; Skotnicki, T.; Bouillon, Pierre; Gentil, P.

doi:10.1109/16.772510

Cited by 43 publications

(15 citation statements)

References 10 publications

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“…'Channel engineering' refers to adding dopants to the substrate under the gate and the contacts to improve transistor characteristics. Shortchannel effects, series resistance and threshold voltage are all affected (Thompson et al 1998, Gwoziecki et al 1999). Many compromises are involved in the design of the contacts to the source and the drain and their extensions.…”

Section: Short Channel Experimentsmentioning

confidence: 99%

Physical limits of silicon transistors and circuits

2005

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A discussion on transistors and electronic computing including some history introduces semiconductor devices and the motivation for miniaturization of transistors. The changing physics of field-effect transistors and ways to mitigate the deterioration in performance caused by the changes follows. The limits of transistors are tied to the requirements of the chips that carry them and the difficulties of fabricating very small structures. Some concluding remarks about transistors and limits are presented.

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Section: Short Channel Experimentsmentioning

confidence: 99%

Physical limits of silicon transistors and circuits

2005

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“…In current deep submicron CMOS technology and beyond, pocket implantation [1][2][3][4] appears to be a commonly used strategy for suppressing SCE. However, it presents many inconveniences such as an increase of the body factor and junction capacitance as well as the junction leakage current [5] .…”

Section: Introductionmentioning

confidence: 99%

Performance investigations of novel dual-material gate (DMG) MOSFET with dielectric pockets (DP)

Luan

Liu

Jia

2008

Sci. China Ser. E-Technol. Sci.

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Dual-material gate MOSFET with dielectric pockets (DMGDP MOSFET) is proposed to eliminate the potential weakness of the DP MOSFET for CMOS scaling toward the 32 nm gate length and beyond. The short-channel effects (SCE) can be effectively suppressed by the insulator near the source/drain regions. And the suppression capability can be even better than the DP MOSFET due to the drain bias absorbed by the screen gate. The speed performance and electronic characteristics of the DMGDP MOSFET are comprehensively studied. Compared to the experimental data from Jurczak et al., the DMGDP PMOSFET exhibits good subthreshold characteristics and the on-state current is almost the twice that of the DP PMOSFET. The intrinsic delay of the NMOS reaches 21% greater than the DP MOSFET for 32 nm node. The higher f T of 390 GHz is achieved, which is a 32% enhancement in comparison with the DP MOSFET when the gate length is 50 nm. Finally, the design guideline and the optimal regions of the DMGDP MOSFET are discussed.dual material gate (DMG), dielectric pockets (DP), short-channel effect (SCE), cutoff frequency

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“…The electron mobility is increased in -25]. Channel [26][27][28][29][30]. The channel is interfaced by source/drain extensions having a small junction depth.…”

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confidence: 99%