2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668)
DOI: 10.1109/edssc.2003.1283543
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Optimizations of sub-100 nm Si/SiGe MODFETs for high linearity RF applications

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“…14. Since the flatness of g m vs I ds curves increases with gate height, the linearity of the UnderlapFinFET devices improves drastically with the increase in the gate height [33]- [34].…”
Section: Analog Performancementioning
confidence: 99%