This paper is based on a comprehensive review of the literature and our own studies. We present a summary of the theoretical models and related empirical expressions to evaluate parameters related to the carrier transport within Si/SiGe heterostructures. The models and expressions include the effects of alloy composition and mechanical strain on the band structure of Si/SiGe alloys and the corresponding interfaces. They are presented in a form suitable for implementation in various types of device simulators. Important parameters, such as the band structure of strained or relaxed SiGe, the conduction and valence band offsets in the Si 1−x Ge x /Si 1−y Ge y heterostructures, the effective transport masses and the densities of states, have been calculated and shown to be in good agreement with existing experimental and theoretical results. Analytical expressions of those parameters as a function of Ge composition of the SiGe alloy have been given for strained Si on relaxed Si 1−y Ge y substrate and strained Si 1−x Ge x on Si substrate.

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The performance potential of an 80 nm physical gate length MOSFET with GaAs channel and high-k gate insulator is investigated using Monte Carlo simulations. The results show that such a device could deliver a 100-125% increase in the drive current at both low and high drain biases compared to equivalent Si based MOSFETs. Various transport model enhancements including the Fermi-Dirac statistics and the interface roughness scattering have been systematically studied in order to attain a more realistic prediction of the device performance.

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