Monte Carlo simulations of III–V MOSFETs

Abstract

The performance potential of an 80 nm physical gate length MOSFET with GaAs channel and high-k gate insulator is investigated using Monte Carlo simulations. The results show that such a device could deliver a 100-125% increase in the drive current at both low and high drain biases compared to equivalent Si based MOSFETs. Various transport model enhancements including the Fermi-Dirac statistics and the interface roughness scattering have been systematically studied in order to attain a more realistic prediction of the device performance.

Numerical simulation of electrical characteristics in nanoscale Si/GaAs MOSFETs

“…We note that advanced modeling and simulation, such as quantum mechanical Monte Carlo simulation, quantitatively will result in more accurate prediction on such nanodevices [1,7,8]. Modeling interface roughness and scattering gives us an insight into the problems of potential device application.…”

“…The oxide thickness is fixed at 1.2 nm, the doping concentration of channel and substrate is 3 × 10 18 cm −3 , and the doping concentration of the source and drain is 5 × 10 19 cm −3 performance of Si/GaAs MOSFET [14,15]. Simulation by using, such as Monte Carlo approach with a proper quantum mechanical model will provide more accurate estimation on the electrical characteristics of such nanodevices [7,8].…”

“…For example, FETs fabricated with materials of germanium (Ge) and galliumarsenic (GaAs) are promising for nanoscale metal-oxidesemiconductor FETs (MOSFETs) due to higher carrier mobility, compared with pure silicon (Si) MOSFETs [5][6][7]. MOSFETs with Si/GaAs stacked channel film relatively exhibits a higher on-state current [7][8], compared with pure Si MOSFET. However, it is not easy to integrate devices with III-V or II-VI materials with current complementary metal oxide semiconductors (CMOS) technology.…”

Monte Carlo Simulations of High-Performance Implant Free In$_{0.3}$Ga$_{0.7}$As Nano-MOSFETs for Low-Power CMOS Applications

“…The reported simulations of scaled implant free In Ga As MOSFETs have been carried out using our ensemble MC compound semiconductor device simulator MC/MOS described in detail elsewhere [10], [17]. The MC module includes electron scattering with polar optical phonons, inter-and intravalley optical phonons, nonpolar optical phonons, acoustic phonons, and ionized impurities.…”

“…The recent development of a suitable high-gate dielectric for GaAs with a low interface state density [6], [7] has brought the prospects for manufacturable III-V MOSFETs closer to reality [8]. Previous Monte Carlo (MC) simulation studies have shown that 80 nm gate length In Ga As MOSFETs with a conventional surface-channel architecture could outperform by more than a factor of two the equivalent Si and strained Si counterparts [9], [10]. However, when the conventional In Ga As MOSFETs are scaled down to 35 nm, the performance improvement margin shrinks [9], [11].…”