Optimized latch-up design of a high voltage nLDMOSFET

Abstract

Both drain-side and source-side engineering by adding N ad and P ad layers to obtain a weak snapback characteristic nLDMOS are presented in this work. It is a novel method to reduce trigger voltage(V t1 ) and to increase holding voltage(V h ). These efforts will be very suitable for the HV power management IC applications. Meanwhile, in this work, we will discuss trigger voltage and holding voltage distributions of these novel HV nLDMOS devices.