Both drain-side and source-side engineering by adding N ad and P ad layers to obtain a weak snapback characteristic nLDMOS are presented in this work. It is a novel method to reduce trigger voltage(V t1 ) and to increase holding voltage(V h ). These efforts will be very suitable for the HV power management IC applications. Meanwhile, in this work, we will discuss trigger voltage and holding voltage distributions of these novel HV nLDMOS devices.
A drain-side engineering to LDMOS by doping concentration and length modulations of the N-type adaptive layer to obtain weak snapback characteristic nLDMOS are presented in this work. It's a novel method to reduce trigger voltage(Vu) and to increase holding voltage(Vh). These efforts will be very suitable for the HV power management Ie applications. Meanwhile, in this work, we will discuss trigger voltage, holding voltage and Ron resistance distribution of these novel HV nLDMOS devices.
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