Optimized Silicon AWG With Flattened Spectral Response Using an MMI Aperture

Pathak, Shibnath; Vanslembrouck, Michaël; Dumon, Pieter; Thourhout, Dries Van; Bogaerts, Wim

doi:10.1109/jlt.2012.2231399

Cited by 109 publications

(64 citation statements)

References 16 publications

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“…State 2 and 3 experience -0.9 dB insertion loss and for the other two states (1 and 4) this loss increases to -1.5 dB. This nonuniformity is similar to that of an AWG wavelength mux/demux [4]. The simulated extinction ratio is -18 dB, assuming ideal phase control of each modulator.…”

Section: Simulationmentioning

confidence: 65%

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A fast 4-channel silicon switch using an AWG with 12 carrier depletion modulators

Pathak

Thourhout

et al. 2014

11th International Conference on Group IV Photonics (GFP)

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Section: Simulationmentioning

confidence: 65%

“…The simulation is performed using the integrated design and simulation framework IPKISS [4]. We adapted the AWG simulation to include a variable phase modulation in the arms.…”

Section: Simulationmentioning

confidence: 99%

A fast 4-channel silicon switch using an AWG with 12 carrier depletion modulators

Pathak

Thourhout

et al. 2014

11th International Conference on Group IV Photonics (GFP)

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“…The AWGs are simulated by a semi-analytical model [5] integrated with our design software (IPKISS) [8]. As we want to illustrate the effect on the crosstalk due to the phase errors introduced by the grid snapping we didn't include any stochastic phase error due sidewall roughness.…”

Section: Simulationmentioning

confidence: 99%

Effect of mask grid on SOI arrayed waveguide grating performance

Pathak

Vanslembrouck

Dumon

et al. 2013

10th International Conference on Group IV Photonics

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“…To realize the rib, a shallow etch step of 70nm is used. This etch step is also used to realize input and output fiber grating couplers as well as the star-coupler of the AWG 5 . An AWG consist of two free propagation regions (which are known as star-couplers) and an array of waveguides with successive increment of length.…”

Section: Fabrication Design and Characterization Of The Photonic Devicementioning

confidence: 99%

A Compact Integrated 40Gb/s Packet Demultiplexer and Label Extractor on Silicon-on-Insulator for an Optical Packet Switch

Heyn¹,

Luo²,

Trita³

et al. 2013

39th European Conference and Exhibition on Optical Communication (ECOC 2013)

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We demonstrate a compact 40Gb/s 32-channel packet demultiplexer and in-band label extractor based on photonic integrated AWG followed by a narrow-band microring resonator at each AWG output. Error free operation with ≤0.5dB penalty was measured. . Introduction Several research projects 1 investigated large port-count and low latency optical packet switches (OPS) in order to flatten the data center network (DCN) and thus to eliminate the communication bottleneck of current DCNs tree topology. However, all the architectures presented employ a centralized controller that leads to port-count dependent reconfiguration time of the switch. Scaling these architectures to thousands of ports will result in high switch configuration time and thus high latency. The numerical and experimental demonstration of a novel modular WDM optical packet switch architecture was demonstrated 2,3 . Each module forwards the M WDM packets to the M output ports based on the information carried by the optical label. The optical label (one for each WDM payload) is transmitted in-band with the optical payload to maximize the optical spectral efficiency and to allow an asynchronous and easier extraction of the label. Each module includes an arrayed waveguide grating (AWG) WDM packet demultiplexer, narrow band fiber Bragg grating filters as optical label extractors, 1xN optical switches, and a switch controller (see Fig. 1). Although the modular OPS architecture has been demonstrated by using off-the shelf discrete components, photonic integration of such complex systems is necessary to decrease drastically the size, unit cost and power consumption. In this paper we bring the realization of an integrated full-functional OPS one step further by demonstrating a silicon photonic integrated device that includes a 32x200 GHz AWG 40Gb/s packet demultiplexer and a narrow band microring resonator (MRR) for label extraction at each of the AWG output waveguides. The chip is fabricated in the high-contrast material system silicon-on-insulator (SOI) to realize ultra compact circuits with small bending radii (<5mm). Experimental results confirmed a channel crosstalk lower than 18 dB and error-free operation less than 0.5dB penalty after the AWG and the label extractor filtering. Also the label, modulated at 1.3Gb/s has been error-free detected after the label extracted with a power penalty of 0.5dB. Fabrication, design and characterization of the photonic deviceOur design is fabricated on a SOI platform exhibiting a 220nm thick silicon device layer on a 2µm thick buried oxide layer. The label extracting MRR must be very narrow band in order to not distort the payload and to minimize the crosstalk of the payload on the label. Using rib waveguides, one can reduce the influence of the sidewall roughness and therefore minimize backscattering which ultimately limits the Qfactor of a MRR on SOI using strip waveguides 4 . To realize the rib, a shallow etch step of 70nm is used. This etch step is also used to realize input and output fiber grating couplers a...

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Optimized Silicon AWG With Flattened Spectral Response Using an MMI Aperture

Cited by 109 publications

References 16 publications

A fast 4-channel silicon switch using an AWG with 12 carrier depletion modulators

A fast 4-channel silicon switch using an AWG with 12 carrier depletion modulators

Effect of mask grid on SOI arrayed waveguide grating performance

A Compact Integrated 40Gb/s Packet Demultiplexer and Label Extractor on Silicon-on-Insulator for an Optical Packet Switch

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