Optimized strained Si/strained Ge dual-channel heterostructures for high mobility P- and N-MOSFETs

Lee, M.L.; Fitzgerald, Eugene A.

doi:10.1109/iedm.2003.1269314

Cited by 34 publications

(18 citation statements)

References 9 publications

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“…A decrease in the enhancement factor at higher effective fields can be ascribed to more significant surface roughness at the oxide/SGOI interface due to the partial strain relaxation. The obtained enhancement factor of 10 in the thick device with a surface-channel structure is consistent with published data for buried-channel Ge pMOSFETs (the enhancement factor of 10 [2] and 20 [3]) with comparable strain on relaxed SiGe virtual substrates. This result indicates that the Ge-condensed SGOI channels can provide hole mobility as high as that expected for epitaxially grown strained SiGe layers.…”

Section: Resultssupporting

confidence: 91%

High-mobility strained SiGe-on-insulator pMOSFETs with Ge-rich surface channels fabricated by local condensation technique

Tezuka

Nakaharai

Moriyama

et al. 2005

IEEE Electron Device Lett.

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A new approach to form strained SiGe-on-insulator (SGOI) channel transistors, allowing fabrication of MOSFETs with very high Ge fraction in selected areas on a silicon-on-insulator substrate, is demonstrated. This method consists of epitaxial growth of an SiGe layer with a low Ge fraction and local oxidation processes. An obtained SGOI pMOSFET with a Ge fraction of 0.93 exhibits up to a tenfold enhancement in mobility. It is also found that MOSFETs having strained SGOI channels with thicknesses of less than 5 nm exhibit hole-mobility enhancement factors of over two. These results indicate that the local SGOI channels fabricated by the proposed technique are promising for implementation of high-mobility SiGe or Ge-channel MOSFETs in system-on-chip (SoC) devices.Index Terms-Mobility enhancement, SiGe MOSFET, silicon-on-insulator (SOI) technology, strained SiGe channel, surface-channel MOSFET, ultrathin body SOI.

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Section: Resultssupporting

confidence: 91%

High-mobility strained SiGe-on-insulator pMOSFETs with Ge-rich surface channels fabricated by local condensation technique

Tezuka

Nakaharai

Moriyama

et al. 2005

IEEE Electron Device Lett.

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“…Figure 6 compares effective mobility in bulk MOSFETs for (a) electrons in strained Si/relaxed SiGe and (b) holes in Si-channel and strained Si/Si 1Ày Ge y dual-channel heterostructures. Dual-channel heterostructures [ Figure 5(b)] use a combination of strained Si and strained Si 1Ày Ge y to enable simultaneously high electron and hole mobilities [23][24][25]. In addition, because of the high Ge content and compressive strain, these structures offer significantly higher hole mobility than either biaxialtensile strained Si [ Figure 6(b), * ] or process-induced Intrinsic delay (s) 10 1,000 100 10 Ϫ10 10 Ϫ11 10 Ϫ12 10 Ϫ13…”

Section: Strain and New Channel Materialsmentioning

confidence: 99%

Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations

et al. 2006

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“…In the literature we can find very important articles on the improvements brought about by the use of the strained silicon or the importance of using the heterostructure [9], [15], but the majority of the works concentrate on the physics and the operation principle as well as the improvements In terms of mobility. The particularity of our work is that it also covers other important parameters that contribute to good DC analysis of strained devices.…”

Section: Resultsmentioning

confidence: 99%

Modeling and Simulation of Biaxial Strained P-MOSFETs: Application to a Single and Dual Channel Heterostructure

Taberkit¹,

Guen-Bouazza²,

Bouazza³

2018

IJECE

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The objectives of this work are focused on the application of strained silicon on MOSFET transistor. To do this, impact and benefits obtained with the use of strained silicon technology on p-channel MOSFETs are presented. This research attempt to create conventional and two-strained silicon MOSFETs fabricated from the use of TCAD, which is a simulation tool from Silvaco. In our research, two-dimensional simulation of conventional MOSFET, biaxial strained PMOSFET and dual channel strained P-MOSFET has been achieved to extract their characteristics. ATHENA and ATLAS have been used to simulate the process and validate the electronic characteristics. Our results allow showing improvements obtained by comparing the three structures and their characteristics. The maximum of carrier mobility improvement is achieved with percentage of 35.29 % and 70.59 % respectively, by result an improvement in drive current with percentage of 36.54 % and 236.71 %, and reduction of leakage current with percentage of 59.45 % and 82.75 %, the threshold voltage is also enhaced with percentage of: 60 % and 61.4%. Our simulation results highlight the importance of incorporating strain technology in MOSFET transistors.

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Optimized strained Si/strained Ge dual-channel heterostructures for high mobility P- and N-MOSFETs

Cited by 34 publications

References 9 publications

High-mobility strained SiGe-on-insulator pMOSFETs with Ge-rich surface channels fabricated by local condensation technique

High-mobility strained SiGe-on-insulator pMOSFETs with Ge-rich surface channels fabricated by local condensation technique

Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations

Modeling and Simulation of Biaxial Strained P-MOSFETs: Application to a Single and Dual Channel Heterostructure

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